Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2000-11-21
2004-01-06
Baker, Stephen M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06675333
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates in general to integrated circuits, and more particularly to serial data communication interfaces and architectures.
BACKGROUND OF THE INVENTION
Advance circuit design techniques have resulted in increasingly complex circuits, both at the integrated circuit and printed circuit board level of electronic design. Diminished physical access is an unfortunate consequence of denser designs and shrinking interconnect pitch. Testability is needed, so that the finished product is still both controllable and observable during test and debug. Any manufacturing defect is preferably detectable during final test before product is shipped. This basic necessity is difficult to achieve for complex designs without taking testability into account in the logic design phase, so that automatic test equipment can test the product. Exemplary test architectures are disclosed in U.S. patent application Ser. Nos. 07/391,751 and 07/391,801, to Whetsel, both filed Aug. 9, 1989, and the entire issue of the
Texas Instruments Technical Journal
, Vol. 5, No. 4, all of which are incorporated by reference herein.
Some existing test bus interfaces allow serial data to be shifted in and out of integrated circuits to facilitate testing of the logic in the device. These buses are designed primarily to transfer a single pattern of serial data into a selected scan path of the integrated circuit once per shift operation. However, in some applications, it may be required to utilize a serial test bus to load or unload a local memory in the integrated circuit. Since memories contain multiple data storage locations, multiple data patterns must be input using multiple shift operations. As a result, transferring data patterns into or out of memory is extremely time consuming due to the multiple shift operations.
Therefore, a need has arisen in the industry for a serial data input and output method which allows devices to be accessed in a more efficient manner than previously achieved.
SUMMARY OF THE INVENTION
In accordance with the present invention, a data communication interface is provided which substantially eliminates or prevents the disadvantages and problems associated with prior interface devices.
In the present invention, a data communication interface is provided for communication with a device. The data communication device includes bus circuitry for transferring data, storage circuitry coupled to the device and to the bus circuitry, and test interface circuitry operable to shift data between the bus and the device. Device access control circuitry is operable to transfer data between the device and the storage circuitry responsive to a control signal.
The present invention provides the technical advantage of allowing efficient communication with a device. The invention is compatible with existing interface structures and requires only minimal additional hardware.
REFERENCES:
patent: 3873818 (1975-03-01), Barnard
patent: 3976940 (1976-08-01), Chau et al.
patent: 4023142 (1977-05-01), Woessner
patent: 4066882 (1978-01-01), Esposito
patent: 4146835 (1979-03-01), Chnapko et al.
patent: 4264807 (1981-04-01), Moen et al.
patent: RE31056 (1982-10-01), Chau et al.
patent: 4357703 (1982-11-01), Van Brunt
patent: 4366478 (1982-12-01), Masuda et al.
patent: 4390969 (1983-06-01), Hayes
patent: 4426697 (1984-01-01), Petersen et al.
patent: 4439858 (1984-03-01), Petersen
patent: 4488259 (1984-12-01), Mercy
patent: 4493077 (1985-01-01), Agrawal et al.
patent: 4494066 (1985-01-01), Goel et al.
patent: 4498172 (1985-02-01), Bhavsar
patent: 4503536 (1985-03-01), Panzer
patent: 4513373 (1985-04-01), Sheets
patent: 4513418 (1985-04-01), Bardell, Jr. et al.
patent: 4519078 (1985-05-01), Komonytshy
patent: 4553090 (1985-11-01), Hatano et al.
patent: 4575674 (1986-03-01), Bass et al.
patent: 4587609 (1986-05-01), Boudreau et al.
patent: 4594711 (1986-06-01), Thatte
patent: 4597042 (1986-06-01), d'Angeac
patent: 4598401 (1986-07-01), Whelan
patent: 4602210 (1986-07-01), Fasang et al.
patent: 4621363 (1986-11-01), Blum
patent: 4627018 (1986-12-01), Trost et al.
patent: 4638313 (1987-01-01), Sherwood, Jr. et al.
patent: 4646298 (1987-02-01), Laws et al.
patent: 4672307 (1987-06-01), Breuer et al.
patent: 4679192 (1987-07-01), Vanbrabant
patent: 4680539 (1987-07-01), Tsai
patent: 4680733 (1987-07-01), Duforestel et al.
patent: 4694293 (1987-09-01), Sugiyama et al.
patent: 4698588 (1987-10-01), Hwang et al.
patent: 4701916 (1987-10-01), Naven et al.
patent: 4701921 (1987-10-01), Powell et al.
patent: 4710931 (1987-12-01), Bellay et al.
patent: 4710933 (1987-12-01), Powell et al.
patent: 4745355 (1988-05-01), Eichelberger et al.
patent: 4764926 (1988-08-01), Knight et al.
patent: 4777616 (1988-10-01), Moore et al.
patent: 4783785 (1988-11-01), Hanta
patent: 4791358 (1988-12-01), Sauerwald et al.
patent: 4799004 (1989-01-01), Mori
patent: 4799052 (1989-01-01), Near et al.
patent: 4802163 (1989-01-01), Hirabayashi
patent: 4821269 (1989-04-01), Jackson et al.
patent: 4833395 (1989-05-01), Sasaki et al.
patent: 4833676 (1989-05-01), Koo
patent: 4857835 (1989-08-01), Whetsel, Jr.
patent: 4862072 (1989-08-01), Harris et al.
patent: 4866508 (1989-09-01), Eichelberger et al.
patent: 4870345 (1989-09-01), Tomioka et al.
patent: 4872169 (1989-10-01), Whetsel, Jr.
patent: 4875003 (1989-10-01), Burke
patent: 4878168 (1989-10-01), Johnson et al.
patent: 4879717 (1989-11-01), Sauerwald et al.
patent: 4887262 (1989-12-01), van Veldhuizen
patent: 4887267 (1989-12-01), Kanuma
patent: 4894830 (1990-01-01), Kawai
patent: 4899273 (1990-02-01), Omoda et al.
patent: 4903266 (1990-02-01), Hack
patent: 4912633 (1990-03-01), Schweizer et al.
patent: 4912709 (1990-03-01), Teske et al.
patent: 4931722 (1990-06-01), Stoica
patent: 4935868 (1990-06-01), Dulac
patent: 4937826 (1990-06-01), Gheewala et al.
patent: 4943966 (1990-07-01), Giunta et al.
patent: 4945536 (1990-07-01), Hancu
patent: 4956602 (1990-09-01), Parrish
patent: 4974192 (1990-11-01), Face et al.
patent: 4974226 (1990-11-01), Fujimori et al.
patent: 4989209 (1991-01-01), Littlebury et al.
patent: 5001713 (1991-03-01), Whetsel
patent: 5014186 (1991-05-01), Chisholm
patent: 5056093 (1991-10-01), Whetsel
patent: 5056094 (1991-10-01), Whetsel
patent: 5084814 (1992-01-01), Vaglica et al.
patent: 5107489 (1992-04-01), Brown et al.
patent: 5115435 (1992-05-01), Langford, II et al.
patent: 5128664 (1992-07-01), Bishop
patent: 5133062 (1992-07-01), Joshi et al.
patent: 5159465 (1992-10-01), Maemura et al.
patent: 5165022 (1992-11-01), Erhard et al.
patent: 5167020 (1992-11-01), Kahn et al.
patent: 5187795 (1993-02-01), Balmforth et al.
patent: 5214760 (1993-05-01), Hammond et al.
patent: 5218702 (1993-06-01), Kirtland
patent: 5276807 (1994-01-01), Kodama et al.
patent: 5329471 (1994-07-01), Swoboda et al.
patent: 5430735 (1995-07-01), Sauerwald et al.
patent: 5495487 (1996-02-01), Whetsel, Jr.
patent: 5632029 (1997-05-01), Bruce et al.
patent: 5687179 (1997-11-01), Whetsel, Jr. et al.
patent: 5802270 (1998-09-01), Ko et al.
patent: 5805792 (1998-09-01), Swoboda et al.
patent: 5905738 (1999-05-01), Whetsel
patent: 6085344 (2000-07-01), Whetsel, Jr. et al.
patent: 0136174 (1985-04-01), None
patent: 0148403 (1985-07-01), None
patent: 0190494 (1986-08-01), None
patent: 0195164 (1986-09-01), None
patent: 0273821 (1988-07-01), None
patent: 0310152 (1989-04-01), None
patent: 57-209546 (1982-12-01), None
patent: 58-155599 (1983-09-01), None
patent: 59-210382 (1984-11-01), None
patent: 60-252958 (1985-12-01), None
patent: 62-228177 (1987-10-01), None
patent: 63-973169 (1988-04-01), None
patent: 1-43773 (1989-02-01), None
patent: 64-79673 (1989-03-01), None
patent: 1-110274 (1989-04-01), None
patent: 1-170873 (1989-07-01), None
patent: 2-16642 (1990-01-01), None
patent: WO 88/04097 (1988-06-01), None
Breuer et al., “A Test and Maintenance Controller for a Module Containing Testable Chips”, 1988 International Test Conference, pp. 502-513.*
van Riessen et al., “Design and Implementation of a Hierarchical Testable Architecture Using the Boundary Scan Standard”, 1s
Ashmore, Jr. Benjamin H.
Whetsel, Jr. Lee Doyle
Baker Stephen M.
Bassuk Lawrence J.
Brady W. James
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
LandOfFree
Integrated circuit with serial I/O controller does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit with serial I/O controller, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit with serial I/O controller will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3252700