Integrated circuit with serial test interface and logic for load

Details Integrated circuit with serial test interface and logic for load Integrated circuit with serial test interface and logic for load

1998-06-08

2000-09-26

Tu, Christine

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

G01R 3128

Patent

active

061254630

ABSTRACT:
Integrated circuit component with terminals for connection to an external communication channel or bus, serial test interface and a configuration register whose content defines operational modes of the integrated circuit, in which the configuration register is loaded with a default configuration, applied externally, through the serial test interface in the course of an initializing phase in which a reset signal applied to the integrated circuit is asserted and in which the default configuration is modifiable via SW or FW, through the external communication channel when the reset signal is deasserted.

REFERENCES:
patent: 5333139 (1994-07-01), Sturges
patent: 5377198 (1994-12-01), Simpson et al.
patent: 5708773 (1998-01-01), Jeppesen, III et al.
patent: 5805607 (1998-09-01), Khu
patent: 5887001 (1999-03-01), Russell

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