Integrated circuit with on-chip data checking resources

Details Integrated circuit with on-chip data checking resources Integrated circuit with on-chip data checking resources

1999-12-30

2003-10-14

Baderman, Scott (Department: 2184)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S722000, C714S768000, C714S005110

Reexamination Certificate

active

06633999

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to integrated circuits having non-volatile memory, such as read-only memory (“ROM”); and more particularly to on-chip resources supporting the manufacturing and testing of data stored in the non-volatile memory.
2. Description of Related Art
The manufacturing of integrated circuit devices including on-chip non-volatile memory, such as mask ROM, includes a step of testing the data stored in the non-volatile memory. Thus, after the data is stored in the non-volatile memory, that data is downloaded into a memory tester which includes a comparator and a buffer memory storing a correct copy of the data. This environment is schematically illustrated in
FIG. 1
, for the case in which the integrated circuit consists of a ROM device. Thus, as shown in
FIG. 1
, a ROM
10
being manufactured is coupled to a memory tester
11
. The memory tester
11
includes a large data buffer memory
12
and a comparator
13
. Addresses are supplied as indicated by arrow
14
to the ROM, and as indicated by arrow
15
to the memory tester
11
. The data supplied from the ROM
10
as indicated by arrow
16
is also supplied to the memory tester
11
. The memory tester compares the correct data from the data buffer memory with the data out from the ROM
10
, and generates a pass/fail flag
17
to indicate whether the data was successfully stored in the ROM
10
.
The approach of the prior art is satisfactory for smaller and slower ROM devices. However, as the size of the data set stored in the ROM increases, the size of the data buffer memory
12
also increases to a prohibitive degree. Furthermore, the testing equipment uses the same address as the ROM chip for accessing the data within the buffer memory
12
. During a testing sequence, only one entry can be stored per address in the buffer memory
12
. Thus, the tester cannot be used for testing ROMs with more than one data set in a single manufacturing sequence, regardless of the size of the buffer memory
12
.
In addition, as the speed of the integrated circuit increases, noise problems encountered in the testing environment during transfer of the data from the ROM to the memory tester interfere with the successful testing of the devices. The testing speeds can be reduced in order to reduce the problem with the noise in the testing environment. However, slower testing with large data sets increases the time involved, and therefore significantly increases the cost of manufacturing.
Accordingly, it is desirable to provide an integrated circuit and a process which supports more efficient testing of data stored in the memory on the integrated circuit.
SUMMARY OF THE INVENTION
The present invention provides an integrated circuit with on chip resources to support the testing of data stored on the integrated circuit. In particular, logic is provided on the integrated circuit to compute a check code using data, or a combination of data and addresses, of a particular data set stored on the device. The check code is compared with a test code produced using a correct version of the particular data set, to indicate whether the particular data set was successfully stored on the device. In one embodiment, an on chip store, such as a ROM, a RAM, an EPROM or the like, is used to hold the code produced using the correct version, and an on chip comparator is used to produce a flag indicating the success or failure of the test. This way, during manufacturing of the device, the memory tester simply tests the flag. The test does not store the entire data set, and does not perform a comparison across the entire data set. Very large data sets, such as data greater than 100 Megabits (Mb), or greater than 500 Mb, can be manufactured and effectively tested in this manner. Also, very fast memory devices can be tested with the support of the on chip resources with some immunity from the noise of the testing environment.
In various embodiments, the check code is computed using a portion of the particular data set in the device, or all of the particular data set. In another embodiment, address logic is included on the integrated circuit, to produce the addresses used for producing the check code. Also in various embodiments, the logic used for computing the check code comprises a cyclic redundancy code generator, a hash function generator, a logical byte-wide or word-wide summing network, or other functional logic.
The structure of the present invention supports a method for manufacturing integrated circuits that include on chip memory. The method includes producing an integrated circuit, and computing the check code using on chip logic in response to data of the particular data set stored in the memory. The process further includes comparing the check code with a test code computed using a correct version of the particular data set. As mentioned before, the process may include storing a test code on the integrated circuit, and comparing the check sum with the test code using on chip logic.
In various embodiments, the process includes supplying the computed check sum to the memory tester, or supplying only the flag to the memory tester.
In another embodiment, the test code is stored on the integrated circuit, and resources are provided to allow an external device to read the test code. Thus, the test code may be utilized for the purposes of sorting integrated circuit die manufactured according to the present invention.
The present invention provides a method for manufacturing integrated circuits that comprises executing a sequence of processes to produce an integrated circuit die on a substrate, using a mask set having a plurality of reticles per mask for forming a corresponding plurality of die per mask, in which at least a first mask in the mask set defines a first data set, and at least a second mask in the mask set defines a second data set. In this manner, a single mask set can be used to produce integrated circuits having variant data sets stored thereon, in a single manufacturing run. On chip resources for storing a test code, and for producing a check code in response to data stored the die are provided. On chip logic is provided for comparing the check code to the test code to produce a signal indicating that valid data has been stored. During testing of integrated circuit, a step of checking the signal is used to verify that one of the first and second data sets stored on the device was successfully formed. Furthermore, the integrated circuit die may be sorted according to the stored test code.
In one embodiment, the integrated circuit comprises a mask ROM storing greater than 100 Mb of data, and more preferably greater than 500 Mb of data. In another embodiment, the integrated circuit comprises a processor including on chip code memory. In various embodiments, integrated circuits including on chip memory for a variety of applications include the self check resources of present invention.
Other aspects and advantages of the present invention can be seen upon review of the figures, the detailed description and the claims which follow.


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