Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-11-10
2003-03-25
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
Reexamination Certificate
active
06539507
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an apparatus for evaluating the state of an IEEE 1149.1 compliant integrated circuit (IC), in a non-test-environment, to detect errors in the integrated circuit and determine the cause of such errors while the integrated circuit is in a system environment while at the same time preserving access to, and functionality of, standard test access port hardware.
BACKGROUND OF THE INVENTION
The IEEE 1149.1 standard provides for standardized provisions on an integrated circuit to allow evaluation of the state of the integrated circuit in a test environment, removed from the system environment and placed on a tester block, to determine chip malfunctions and the cause thereof. While evaluation of an integrated circuit in a test environment is useful, it limits the ability to evaluate the integrated circuit behavior that actually occurs while in a system (non-test) environment.
One system and technique of evaluating the state of an integrated circuit is shown in FIG.
1
. In this system an external tester device
11
is connected to the integrated circuit
10
and utilized to issue commands and control the integrated circuit
10
via the standard test access port (TAP)
20
. The tester
11
controls the clock signal TCK, the mode select signal TMS and the reset or control signal TRST_N and inputs known data signals via TDI. More particularly, the TAP includes a state machine
22
and a scan select
21
. The state machine
22
generates a series of known state signals in response to input from tester device
11
. The known state signals generated by the state machine
22
are output via TAP access unit
40
to the scannable state register (
30
a
-
30
e
) selected (addressed) by scan select
21
. These known state signals are then shifted thru the selected state register while the output of the selected state register is monitored and obtained by test device
11
via output TDO to determine if any errors have occurred and, if so, what the cause may be.
FIG. 2
illustrates TAP access unit
40
in more detail. It will be noted that in this example scannable state register unit
30
incorporates five separate state registers
30
a
,
30
b
,
30
c
,
30
d
and
30
e
. However, at any one time, only a single selected (addressed) state register is selected (or addressed). In order to simplify discussions herein,
FIG. 2
illustrates provisions for enabling only a single one of the state registers
30
a
,
30
b
,
30
c
,
30
d
or
30
e
, in this example, state register
30
a
is shown and discussed. It will be understood by those skilled in the art, that the illustrated provisions are actually duplicated for each of the state registers
30
a
,
30
b
,
30
c
,
30
d
or
30
e
in an actual integrated circuit
10
. Further it will be recognized that any number of state registers can be utilized provided that TAP
20
, and more particularly, scan select
21
, can provide for addressing each one.
A reset signal TRST_N is provided from tester
11
to each of gates
410
,
420
,
430
, and
440
to initialize and enable functionality of test access port
20
. When the test access port
20
is enabled, signal TDI from tester
11
is then provided to state register unit
30
via gate
410
, as a known data input signal.
Scannable state register unit
30
is composed of multiple scannable state registers
30
a
-
30
e
, each having parallel data inputs and a serial scan input. The scannable state register
30
a
-
30
e
alternately operate in two modes: normal mode and test mode. The mode that the scannable state register operates in is determined by the input signal NORM. The scannable state registers
30
a
-
30
e
are each clocked via clock signals from gated clock
70
during normal mode.
During test mode the clock
70
is stopped. In normal mode, the scannable state register function normally as required by system operations. In normal mode, the state registers respond to each clock signal by inputting data on the parallel data bus into the register. Scannable state register unit
30
may be implemented in different forms. For purposes of discussion, the example of a state register composed of a master node and a slave node is presented.
Signal WNORM from state machine
22
is input to scan register
30
via gate
420
as signal NORM which controls whether scannable state register unit
30
operates in normal mode, as if it is in its system environment and responsive to its parallel data inputs, or in test mode wherein it is responsive to the serial scan input SIN. SCAN_SEL (a) is received from scan select
21
to enable gate
430
and allow output of WSHIFT from state machine
22
as master shift signal NSFTMA(a). To enable (select) circuitry relevant and necessary to shifting data through the selected one of the state registers
30
a
-
30
e
. Gate
430
receives an input signal WSHIFT from state machine
22
. Provided SCAN_SEL (a) has been enabled, a master shift signal NSFTMA is generated and output via gate
430
to selected state register
30
a
to actuate, for example, a master node of state register
30
a
. With reference to gate
440
, input signal WNNSHIFT is received from state machine
22
. Provided SCAN_SEL (a) has been enabled, the state register
30
a
slave shift signal, NSFTSL, is output via gate
440
to actuate, for example, a slave node of a master-slave register configuration, which state register
30
a
may, for example, be implemented as, to shift data through the master-slave register configuration.
WSHIFT from state machine
22
provides state data to the selected state register
30
a
. During the shifting of state register
30
a
an output SOUT is obtained from the selected state register
30
a
and output to tester
11
via gate
450
for evaluation.
The disadvantage of this system is that it is only useful, or applicable, where the integrated circuit is in an environment in which the standard IEEE 1149.1 test access port (TAP) can be accessed and controlled. In a typical system environment, the TAP
20
is not accessible and in fact relevant inputs of the TAP
20
are held to ground level to disable the TAP
20
while the integrated circuit is in the system environment. As a result, if an integrated circuit has a malfunction that occurs only during operation in a system environment, there is no way to access and evaluate the state of the chip to determine the cause of the problem. In order to alleviate the need for removing the integrated circuit from the system environment in order to evaluate the integrated circuit the use of supplementary external hardware, included as a part of the system environment, has been proposed. Unfortunately, the addition of this supplementary external hardware is not always feasible, or possible, due to cost or system constraints. Further, while the use of proposed supplemental external hardware does allow for maintaining access to, and use of, the TAP while the integrated circuit is in a non-test environment, it introduces the risk of corruption of internal state register data during the testing process, due to the fact that the control lines for the TAP are directly controlled, or manipulated, via the external hardware. Thus, a heretofore unaddressed need exists in the industry to address the aforementioned deficiencies and inadequacies.
SUMMARY OF THE INVENTION
The present invention provides for an integrated circuit having provisions for evaluating the state of the integrated circuit. The integrated circuit incorporates a test access port and a user addressable control register. There is also provided a switching unit to allow for alternate switching between the test access port and the user addressable control register. A state register is provided which receives input from, and is controlled by, the selected one of the test access port or the user addressable control register.
The present invention seeks to provide for evaluation of an integrated circuit either in a system environment or a test environment without the necessity for the implementation of external hardware. Further, th
Beucler Dale R
Bower Kenneth S
Buck-Gengler Joel
Diehl Michael R
Fiscus Randy L
Agilent Technologie,s Inc.
Tu Christine T.
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