Integrated circuit with self-testing circuit

Details Integrated circuit with self-testing circuit Integrated circuit with self-testing circuit

2006-05-02

2006-05-02

Tu, Christine T. (Department: 2138)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S732000

Reexamination Certificate

active

07039844

ABSTRACT:
An integrated circuit (14) with an application circuit (1) to be tested and a self-testing circuit (5-13), which is provided for testing the application circuit (1) and generates pseudorandom test patterns, which can be transformed, by means of first logic gates (6, 7, 8) and signals externally fed to said gates, into deterministic test vectors, which are fed to the application circuit (1) for testing purposes, wherein the output signals occurring through the application circuit (1) as a function of the test patterns are evaluated by means of a signature register (13), wherein, by means of second logic gates (10, 11, 12) and signals fed to said gates, those bits of the output signals of the application circuit (1) which, due to the circuit structure of application circuit (1), have undefined states, are blocked during testing.

REFERENCES:
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patent: 6370664 (2002-04-01), Bhawmik
patent: 1 178 322 (2002-02-01), None
patent: WO 01 038889 (2001-05-01), None
Kiefer, G, et al. “Using Bist Control for Pattern Generation” Proceedings of the International Test Conf. ITC '97. Washington, DC No. 1-6, 1997, International Test Conf., New York, NY: IEEE, US, vol. Conf. 28, Nov. 1, 1997.

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