Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2010-11-02
2011-11-01
Gaffin, Jeffrey A (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S727000, C714S729000
Reexamination Certificate
active
08051348
ABSTRACT:
An integrated circuit includes logic circuits including the first and second logic circuits, and a scan chain configured to test the logic circuits. The scan chain includes the first scan chain portion for testing the first logic circuit based on an input test pattern and output the first output test pattern, a switching unit for selecting and outputting one of the input test pattern and the first output test pattern as a selected test pattern, and the second scan chain portion for testing the second logic circuit based on the selected test pattern from the switching unit and output the second output test pattern. The switching unit selects one of the input test pattern and the first output test pattern based on at least one of a logic depth, a number of gates, a number of gate inputs and a number of gate outputs of the logic circuits.
REFERENCES:
patent: 5034986 (1991-07-01), Karmann et al.
patent: 5043986 (1991-08-01), Agrawal et al.
patent: 5504756 (1996-04-01), Kim et al.
patent: 5592493 (1997-01-01), Crouch et al.
patent: 5828579 (1998-10-01), Beausang
patent: 5867036 (1999-02-01), Rajsuman
patent: 6370664 (2002-04-01), Bhawmik
patent: 6415404 (2002-07-01), Asou
patent: 6434733 (2002-08-01), Duggirala et al.
patent: 6480980 (2002-11-01), Koe
patent: 6490702 (2002-12-01), Song et al.
patent: 6516432 (2003-02-01), Motika et al.
patent: 6560147 (2003-05-01), Yoshiyama
patent: 6615380 (2003-09-01), Kapur et al.
patent: 6658632 (2003-12-01), Parulkar et al.
patent: 6728914 (2004-04-01), McCauley et al.
patent: 6732068 (2004-05-01), Sample et al.
patent: 6836877 (2004-12-01), Dupenloup
patent: 2002/0083386 (2002-06-01), McCauley et al.
patent: 2002/0136064 (2002-09-01), Yoshiyama
patent: 2003/0140293 (2003-07-01), Motika et al.
patent: 2003/0145288 (2003-07-01), Wang et al.
patent: 2004/0128596 (2004-07-01), Menon et al.
patent: 2005/0283690 (2005-12-01), McLaurin
Gaffin Jeffrey A
Marvell Israel (MISL) Ltd.
Merant Guerrier
LandOfFree
Integrated circuit testing using segmented scan chains does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit testing using segmented scan chains, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit testing using segmented scan chains will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4309299