Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1999-11-24
2003-07-29
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S004110, C714S046000
Reexamination Certificate
active
06601200
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Technical Field
This invention generally relates to electronic testing, monitoring, and control, and more specifically relates to integrated circuit testing, monitoring, and control.
2. Background Art
The proliferation of modern electronics into our everyday life is due in large part to the existence, functionality and relatively low cost of advanced integrated circuits. As technology moves ahead, the sophistication of electronic systems increases. An important aspect of manufacturing an advanced electronic system is the ability to thoroughly test the components and subassemblies in the system. The testability of semiconductors was enhanced with the development of boundary-scan testing, as disclosed in IEEE Standard 1149.1 “Standard Test Access Port and Boundary Scan Architecture.” Boundary scan testing allows an integrated circuit to be tested by placing shift registers between functional circuitry and input/output pins when the device is placed in test mode. Test data is typically serially scanned into the shift registers to drive certain inputs, clocks are applied, results are captured, and the resultant outputs are determined by shifting the data out of the registers. The serial shift register elements that make up the boundary scan circuitry is known as a scan chain, because test data may be shifted or “scanned” into or out of the daisy-chained boundary scan registers.
Boundary scan testing requires an external tester that has detailed knowledge regarding the configuration of chips in the scan chain, the test data to be shifted into the scan chain, and the expected results that should be shifted out of the scan chain. As a result, as each new chip and electronic assembly is developed, the test procedure for each chip and for each electronic assembly must be manually derived and programmed into the external tester. Boundary scan testing thus-requires a new custom test-to be defined in the tester for each new chip or assembly that is developed, along with a specific test fixture for each chip and electronic assembly.
Boundary scan testing is beneficial for testing interconnections on an electronic assembly and for static testing of the defined data structures of an integrated circuit. However, boundary scan testing does not support dynanic or “in operation” testing, monitoring, or control of an integrated circuit or electronic assembly. Without a way to test a new chip or electronic assembly without manually defining each new test in an external tester, the effort required to test an integrated circuit or electronic assembly will continue to be a drain on the resources of companies that develop chips and electronic assemblies.
DISCLOSURE OF INVENTION
According to the preferred embodiments, an integrated circuit (i.e., chip under test) includes a control and monitor interface that includes on-chip support for one or more network protocols that allow the chip to be directly coupled to a network. The control and monitor interface defines one or more operations that can be performed on the chip. In a system for testing chips under test, the control and monitor interface of all of the chips under test are coupled to a network, which is also coupled to a control and monitor mechanism. When a chip under test receives a message on the network from the control and monitor mechanism to execute an operation, it performs the requested operation, then reports the results. In this manner much of the intelligence regarding the test can be pushed on-chip, rather than having all of the testing intelligence residing in an external tester. This allows some standardization in tests that are performed from one chip under test to the next.
REFERENCES:
patent: 5321277 (1994-06-01), Sparks et al.
patent: 6425101 (2002-07-01), Garreau
patent: 6449741 (2002-09-01), Organ et al.
Delp Gary Scott
Engbersen Antonius Paulus
Herkersdorf Andreas G.
International Business Machines - Corporation
Martin Derek P.
Martin & Associates L.L.C.
Tu Christine T.
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