I2C bus protocol controller with fault tolerance

Details I2C bus protocol controller with fault tolerance I2C bus protocol controller with fault tolerance

2000-11-20

2004-04-27

Beausoliel, Robert (Department: 2184)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S043000, C716S030000

Reexamination Certificate

active

06728908

ABSTRACT:

ORIGIN OF INVENTION
The invention described herein was made in the performance of work under a NASA contract, and is subject to the provisions of Public Law 96-517 (35 U.S.C. 202) in which the Contractor has elected to retain title.
BACKGROUND
I2C is a bus developed by Philips Semiconductors to connect integrated circuits (ICs). The standard I2C bus may operate as a multi-master bus: Multiple ICs may be connected to the I2C bus and each one may act as a master by initiating a data transfer. Serial 8-bit oriented, bi-directional data transfers may be made at up to 100 kbit/s in a standard mode or up to 400 kbit/s in a fast mode. The I2C bus may include two bus lines, a serial data line (SDL) and a serial clock line (SCL).
The standard I2C bus protocol does not provide certain fault tolerance features. It may be desirable to include an I2C bus controller that may handle such fault tolerance features in ICs connected to an I2C bus. These fault tolerance features may prevent certain errors and faults from interfering with operation of the I2C bus. ICs including such an I2C bus controller may be used in the development and production of systems that require fault tolerance, such as aeronautic and astronautic systems.
SUMMARY
In an embodiment, a bus controller for connecting a device to an Inter-Integrated Circuit (I2C) bus includes fault tolerance features. The I2C bus controller may support fail silent, data transmission error detection, e.g., cyclic redundancy check (CRC), and byte count check operations.
The I2C bus controller may include a control unit connected to an I2C core module having a base address, and glue logic to connect the two components. The I2C bus controller may also include a second I2C core module having a base address plus one (BP
1
), that is, the next available address. The I2C bus controller may also include a mute timer that countdowns a mute timeout period. This mute timer may be reset upon receiving a fail silent test message sent by a master on the I2C bus in slave mode, or in the master mode, from itself through the BP
1
I2C core module. If the mute timeout period expires, the control unit may disable the I2C bus controller from transmitting on the I2C bus. The I2C bus controller may include an unmute timer. In the master mode, the unmute timer may be triggered to countdown an unmute timeout period at the expiration of the mute timeout period. When the timeout period expires, the control unit may re-enable transmission on the I2C bus.
The control unit may format CRC values and byte count values into messages. The I2C bus controller may include a byte counter to compare actual bytes received to the expected byte count indicated by a received byte count value.
The I2C bus controller may interact with nodes on the I2C bus that support the fault tolerance features and with nodes that do not support the fault tolerance features.
The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will be apparent from the description and drawings, and from the claims.


REFERENCES:
patent: 5201054 (1993-04-01), Dudhela
patent: 5694542 (1997-12-01), Kopetz
patent: 6088826 (2000-07-01), Teich
patent: 6154803 (2000-11-01), Pontius et al.
patent: 6233635 (2001-05-01), Son
patent: 6513131 (2003-01-01), Kanekawa et al.
Phillips Semiconductor, “The I2C-bus and how to use it (including specifications)”, pp. 1-24, 4/95.

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