IBIST test for synchronous lines at multiple frequencies

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing

Reexamination Certificate

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Reexamination Certificate

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10689265

ABSTRACT:
A system for testing a synchronous link utilizing a single test pattern sequence. Components coupled via a link are each configured to generate and check test patterns according to a single repeated test pattern sequence. Test patterns which are generated are based upon two simple patterns. Each test cycle, a bit is chosen from one of the two patterns for use in generating the test pattern. A sixteen cycle test pattern sequence is utilized in which values are chosen from one or the other of the two patterns in a predetermined manner. In a bi-directional test, two components which are coupled via a link alternate driving selected values based upon the predetermined sequence. Each component may alternate driving sequences of one or more cycles. An ordering of cycles may be chosen to test various permutations of driver interaction between the respective components.

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