Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2006-07-27
2009-02-17
Torres, Joseph D (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S727000
Reexamination Certificate
active
07493536
ABSTRACT:
An electronic integrated circuit includes a signal path connected between the functional logic and an external input terminal, which signal path includes a memory circuit. The memory circuit is coupled to the input terminal and is selectively operable to detect and resolve voltage contention at the input terminal, and is also selectively operable to isolate itself from voltages at the input terminal. The memory circuit has two data inputs, one from the input terminal and the other from a serial data path. The memory circuit has two control inputs, one to a first switch between the input terminal and an input buffer and the other to a second switch between the serial data path and the input buffer.
REFERENCES:
patent: 5056094 (1991-10-01), Whetsel
patent: 5627839 (1997-05-01), Whetsel
patent: 5715255 (1998-02-01), Whetsel
Bassuk Lawrence J.
Brady W. James
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Torres Joseph D
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