Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1998-06-30
2001-06-12
Wiley, David A. (Department: 2155)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
Reexamination Certificate
active
06247143
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates to multiprocessor computer systems and to processors for such systems. A particular application of the invention is to fault tolerant processing systems.
Many processing systems operate to a strict timing regime, changing their internal state on a known clock. Such a synchronous design of a processing system results in a large finite state machine. The internal state and outputs of this machine are entirely predictable, if inputs are presented in a known relationship to the clock. This determinism enables the construction of a fault tolerant multi-computer system by providing checking hardware, which compares the operation of one processor or set of processors against that of another identical processor or set of processors. The checking hardware can be arranged to check for faults in the operation of one or more of the processing sets by comparing the outputs of those processing sets on each clock.
Other processing systems do not behave in such a simple manner. Examples of this type are processing systems where the clock is not known, where multiple unrelated clocks are used, or where processor operation uses no clocks at all. These processing systems cannot be modelled as synchronous finite state machines. It may not be possible to present inputs to these processing systems in any known relationship to the computer's internal state. The detailed operation of these machines is non-deterministic. This prevents ordinary construction of checking hardware to compare operation between identical systems.
I/O operations may not occur at the same time from the respective processors of processing sets. As a result, I/O operations cannot simply be issued to an external bus on receipt, as a first received I/O operation may or may not be valid.
Accordingly, an aim of the present invention is to provide for the reliable and efficient handling of I/O operations in a multiprocessor system where at least one processor, or set of processors, operates asynchronously of another processor or set of processors.
SUMMARY OF THE INVENTION
Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Combinations of features from the dependent claims may be combined with features of the independent claims as appropriate and not merely as explicitly set out in the claims.
In accordance with one aspect of the invention, there is provided a monitor for a multiprocessor system including a plurality of processing sets, wherein at least one processing set is operable asynchronously of another processing set. The monitor is connectable to receive I/O operations output from the processing sets, and is operable to buffer the I/O operations, to compare an I/O operation output from one processing set to I/O operations buffered for another processing set for determining equivalent operating (i.e. equivalent operation or functioning) of the processing sets, and to issue a state modifying I/O operation only on determining equivalent operating of the processing sets.
An embodiment of the invention can thereby respond to I/O instructions in an efficient manner, directly forwarding I/O operations which are not state modifying (i.e.; where these may be withdrawn if required without corruption if a fault were subsequently determined), and buffering I/O operations prior to being forwarded until equivalent operation has been determined if the I/O operations are state modifying. An embodiment of the invention is thereby able to ensure that I/O operations are only issued from the monitor when the monitor is confident that the I/O operations are valid. Examples of non-repeatable state modifying operations are a read instruction with side effect or a write instruction. By comparison, a read instruction having no side effects could issued directly from the monitor on first receipt from a processing set.
Equivalent operating of the processing sets could be determined by majority voting. As an alternative, equivalent operating of the processing sets could be determined when all processing sets have output the operation. Equivalent operating of the processing sets could be determined in accordance with a policy which varies according to the number of processing sets being monitored.
In order to facilitate control and ordering of I/O operations for issue from the monitor, the monitor is preferably operable:
to determine a buffer for each I/O operation dependent upon first invariant information in the I/O operation;
to determine an order of I/O operations within the identified buffer dependent on second invariant information in the I/O operations; and
to determine equivalent operation of the processing sets on the basis of equivalent third invariant information in the I/O operations at equivalent positions in equivalent buffers for the processing sets.
The first invariant information comprises the processing set and may also comprise one or more parameters of an I/O operation selected from an I/O operation type and a processor number within a processing set. The second invariant information can comprise a parameter of an I/O operation selected from: an address phase ordering and an order number. The third invariant information can comprise one or more parameters of an I/O operation selected from: write value data; an I/O command; and an address.
The monitor can also be arranged to ignore variant information of an I/O operation.
Where each processing set is a symmetric multiprocessor, the monitor can be configured to ensure equivalent ordering of mutexes (mutual exclusion primitives) for the processing sets for controlling access by the processors of respective processing sets to the respective resources, thus maintaining equivalent operating of the processing sets.
In accordance with another aspect of the invention, there is provided a fault tolerant multiprocessor computer system comprising: a plurality of processing sets, wherein at least a first processing set is operable asynchronously of a second processing set; and a monitor as described above.
In accordance with a further aspect of the invention, there is provided a method of operating a fault tolerant multiprocessor computer system comprising a plurality of processing sets, wherein at least a first processing set is operable asynchronously of a second processing set and a monitor connected to receive I/O operations output from the processing sets; the method comprising:
buffering the I/O operations;
comparing an I/O operation output from a processing set to I/O operations buffered for another processing set for determining equivalent operating of the processing sets; and
issuing a state modifying I/O operation only on determining equivalent operating of the processing sets.
REFERENCES:
patent: 5193175 (1993-03-01), Cuhs, Jr. et al.
patent: 5630046 (1997-05-01), Loise
Conley Rose & Tayon PC
Kivlin B. Noäl
Sun Microsystems Inc.
Wiley David A.
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