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System for precoding parity bits to meet predetermined...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
Reexamination Certificate

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System for processing and transmitting digital broadcasting...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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System for protecting the transmission of live data streams,...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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System for protection link supervision

Error detection/correction and fault detection/recovery – Pulse or data error handling – Transmission facility testing
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System for reducing test data volume in the testing of logic...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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System for remapping defective memory bit sets

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Patent

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System for storing data words in a RAM module

Error detection/correction and fault detection/recovery – Pulse or data error handling – Error/fault detection technique
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System for storing device test information on a...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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System for test data storage reduction

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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System for testing a group of functionally independent...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
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System for testing an integrated circuit using multiple test...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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System for testing fast synchronous digital circuits,...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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System for testing IC chips selectively with stored or...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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System for testing multiple devices on a single system and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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System for testing real and simulated versions of an...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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System for verifying signal timing accuracy on a digital...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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System for verifying the effectiveness of a RAM BIST controller'

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Patent

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System including a ferroelectric memory

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Patent

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System including a ferroelectric memory

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
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System initialization of microcode-based memory built-in...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
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