Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
2001-10-05
2004-08-24
Tu, Christine T. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S728000, C703S013000
Reexamination Certificate
active
06782501
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method and system for compressing test data used in the testing of logic products such as integrated circuit chips and the like, to economize on the amount of computer memory, disk storage and time required to test such products.
In the testing of devices utilized in computers, such as combinational logic circuit chips and memory arrays, tester devices are used. To test, for example, a combinational logic circuit, a tester applies stimuli to inputs of the chip, and resulting output responses are observed in order to detect faults in an expected performance of the logic circuit. The detected faults may be used to debug the circuit design.
One method of applying test stimuli to a logic circuit includes placing “scan latches” before and after the combinational logic circuits to be tested. In this method, test data is clocked or scanned from a data input pin to a chain of input latches. The test data typically comprises 0s and 1s which may be arranged as a plurality of vectors. The test vector data comprises “care” bits and “non-care” bits. Care bits are bits which are set by test-generating software to target specific or “focal” faults in the logic being tested. Non-care bits are not targeted toward any particular focal fault. A chain of input latches loaded with test vector data may be referred to as a “scan chain.”
According to the method, application of the test vectors to the combinational logic does not begin until all of the input latches are filled using scan chains. Once all the input latches are filled, the test vectors are released and applied to the combinational logic. The combinational logic processes the test vectors and captures the results in latches, and from there the results are scanned to a test output pin where faults may be detected.
Advances in computer technology have permitted significant increases in the density with which logic circuits can be packed onto a chip, and accordingly, the number of functions and operations that a chip can perform has increased significantly. Attendant to the increased density and number of logic circuits on a chip, there is an increase in the number, complexity and size of test vectors which need to be applied by a tester to fully verify the chip's operation. Along with the increased volume of test vectors are associated costs in computer resources used in generating and storing the test vectors, and in tester memory and time needed to download test data to the tester.
In view of the foregoing, a method and system for efficiently handling test vector data which addresses the noted concerns is needed.
SUMMARY OF THE INVENTION
A method and system according to the present invention provides for highly compressible test vectors to be formed, allowing substantial economies in computer resources, tester memory requirements and test processing time.
According to the new invention, the test response output data are compressed into a much more compact data representation by using error-detecting data compression means. In an embodiment, the response data are compressed into signatures using Cyclic Redundancy Check (CRC) codes. The CRC-based signatures can be generated by hardware that is located in the product under test, inside the tester, or between the product under test and the tester, or by software in the tester. The amount of expected signature data that needs to be stored on the tester for comparison is much smaller than the total amount of test output response data produced by the product under test.
Furthermore, according to the invention, filling the non-care bits in the test input stimulus vector data set with repetitive, repeated, or other algorithmically generated value sequences forms a highly compressible test vector data set. A further reduction in the input stimulus data can be achieved by allowing a substantial portion of the care bits also to be set to repetitive, repeated, or other algorithmically generated value sequences. The proposed combination of data compression techniques for both, test input stimulus data and test output response data, results in significantly better overall data reduction than the use of either method by itself.
In an embodiment, the highly compressible test input stimulus vector data set comprises a differential test vector data set. An “exclusive OR” (XOR) operation may be performed between the original care bits of the test vector data and a background vector data set, to generate the differential vector data set. In the differential data set, a substantial portion of bits corresponding to the original care bits may be set to a value of 0 (zero). Bit positions in the differential vector data set corresponding to the non-care bits of the original test vector data are filled with 0s. The background vector data is constructed in a way that permits easy algorithmic generation of the fill data values from a small amount of initialization data using software residing in the tester and operating while the test is performed, hardware that is located in the product under test, inside the tester, or between the tester and the product under test and is operating while the test is performed, or by software used for preparing the tester program and associated data loaded into the tester prior to testing.
The repetitive values of 0 generated in the differential vector data set increase the compressibility of the differential vector data set. The differential vector data set may be compressed to economize on memory and storage requirements in stages of a testing process, and subsequently decompressed to recover the original care bits of the test vector data set when it is to be loaded into input latches.
A method and system according to the present invention provides for highly compressible test vectors to be formed, allowing substantial economies in computer resources, tester memory requirements and test processing time.
According to the invention, a highly compressible test vector data set is formed by filling the non-care bits in the test vector data set with repetitive or repeated values. A substantial portion of the care bits may also be set to repetitive values.
In an embodiment, the highly compressible test vector data set comprises a differential test vector data set. An “exclusive OR” (XOR) operation may be performed between the original care bits of the test vector data and a background vector data set, to generate the differential vector data set. In the differential data set, a substantial portion of bits corresponding to the original care bits may be set to a value of 0 (zero). Bit positions in the differential vector data set corresponding to the non-care bits of the original test vector data are filled with 0s.
The repetitive values of 0 generated in the differential vector data set increase the compressibility of the differential vector data set. The differential vector data set may be compressed to economize on memory and storage requirements in stages of a testing process, and subsequently decompressed to recover the original care bits of the test vector data set when it is to be loaded into input latches in a tester.
REFERENCES:
patent: 3783254 (1974-01-01), Eichelberger
patent: 4428060 (1984-01-01), Blum
patent: 4498172 (1985-02-01), Bhavsar
patent: 4536881 (1985-08-01), Kasuya
patent: 5377197 (1994-12-01), Patel et al.
patent: 5392298 (1995-02-01), Shinjo
patent: 5544173 (1996-08-01), Meltzer
patent: 5748497 (1998-05-01), Scott et al.
patent: 5831992 (1998-11-01), Wu
patent: 6327687 (2001-12-01), Rajski et al.
IBM Technical Disclosure Bulletin, “Test Time/Data Volume Reduction Technique” T.W. Sehr, vol. 24, No. 5, Oct. 1981; pp. 2560-2562.
IBM Technical Disclosure Bulletin, “Method for Masking Unpredictable Shift Register Latch States During Random Pattern Self-Test”, K.T. Kaliszewski; vol. 36, No. 02, Feb. 1993; pp. 239-241.
Distler Frank O.
Farnsworth L. Owen
Ferko Andrew
Keller Brion L.
Koenemann Bernd K.
Cadence Design Systems Inc.
Orrick Herrington & Sutcliffe
Tu Christine T.
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