Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1997-11-26
2001-02-20
De Cady, Albert (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C324S073100, C326S030000
Reexamination Certificate
active
06192496
ABSTRACT:
MICROFICHE APPENDIX
This specification includes a microfiche appendix in compliance with 37 C.F.R. §1.96(c).
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to system for testing automatic testing machines, and more particularly to method and apparatus for testing the accuracy of signal timing on a digital testing device.
2. Discussion of the Related Art
A variety of automatic test equipment (ATE) have long been known for testing electronic circuits, devices, and other semiconductor and electronic products. Generally, automatic test equipment are divided into two broad categories, analog testers and digital testers. As the names imply, analog testers are generally designed for testing analog circuit devices, while digital testers are designed for testing digital circuit devices. Digital testers, as is known, generally include a testing device having a number of internal circuit cards or channels that generate programmably controlled test signals for testing and evaluating a Device Under Test (DUT). More specifically, ATE are programmably controlled to be adapted or configured to testing a variety of devices in a variety of ways. This is achieved by programming output signals to inject a certain signal (or signal transition) to a certain pin or signal line on a DUT. In this regard, a digital tester generally includes a test head whereby electrical signals are input to and output from the tester. The test head comprises a number of connectors, each defining a channel, which may be connected via cable or otherwise to a device under test. The electronics within the digital tester may then input and output signals to/from a DUT via the test head.
By way of an extremely simple illustration, consider a digital tester that is configured to test a wafer containing, among other things, a two input AND gate. The digital tester may be configured to apply a logic one on the two signal lines that correspond to the inputs of the AND gate, then receive the signal on the signal line corresponding to the output to ensure that it is driven to a logic one. The tester may then be configured to alternatively apply logic zero signals on each of the two signal lines corresponding to the AND gate inputs, in order to verify that the output of the AND gate transitions from a logic one to a logic zero in response. Although such a test will verify the functional operation of the AND gate, additional tests must be executed to verify timing and other aspects of the AND gate.
For example, assume that the two input signals to the AND gate are a logic one and a logic zero, the output is also a logic zero. When, however, the second input transitions from a logic zero to a logic one (whereby both inputs are at a logic one) then the output of the AND gate transitions from a logic zero to a logic one. Furthermore, the output must make this transition within a prescribed period of time, which time will be prescribed by manufacturer specifications. Accordingly, digital testers are further designed to allow programmed testing of such features by sensing and measuring the time between the transition of the input signal to the corresponding transition of the output signal. It will be appreciated that the example given above is an extremely simple example and is presented merely for purposes of illustration, and, as will be appreciated by those skilled in the art, digital testers are much more sophisticated and are capable of performing much more sophisticated and complex testing routines.
An extremely important aspect of ATE, including digital testers, is that the testing equipment maintain extremely accurate tolerances. Otherwise, it will not be clear whether measured values of a DUT reflect errors or discrepancies within the DUT, or whether errors or discrepancies result from component or other tolerance variations in the ATE components. In this regard, automatic test equipment manufacturers generally provide a set of built-in-test (BIT) routines for the automatic test equipment. However, and as will be further described below, these manufacturer provided BIT routines have proven to be generally inadequate in today's market of high-speed components and high volume manufacturing facilities.
Another way of verifying the accurate operation of a tester may be accomplished by using accurate, external testing equipment in a manual fashion. For example, volt meters may be used for testing voltage levels, and a oscilloscopes may be used for evaluating timing aspects. However, it will be appreciated that external testing of an ATE is extremely time consuming, and therefore adversely impacts production quantities. A particular problem that has been noted in recent years specifically relates to a digital tester's ability to self-test for timing accuracy. Indeed, the electronic devices today, which are often configured to operate at clock speeds in the hundreds of megahertz frequency range, must generally be maintained within tolerances on the order of hundreds of picoseconds. As a result, digital testers have generally proven unable to maintain the required accuracy through the manufacturer's test procedures provided with the equipment.
As a result of the general failure of testing devices in this respect, circuit designers have been known to write circuits tests for specific testers. That is, a circuit designer may design an electronic circuit test to pass the testing requirements of a given automatic tester, while failing those same tests on another digital tester of the same type. Charts, sometimes called white boards, have been generated that keep track of certain characteristics of various automatic testing equipment. Circuit designers have used the information contained within these white boards in order to design circuits to pass the test of a given tester. Clearly, however, this approach adversely affects the overall yield of a designed product, and is disfavored.
Accordingly, there is a need to develop a system for improving the accuracy of automatic testing equipment, specifically digital testers, by verifying with a high degree of accuracy the performance of the digital testers.
SUMMARY OF THE INVENTION
Certain objects, advantages and novel features of the invention will be set forth in part in the description that follows and in part will become apparent to those skilled in the art upon examination of the following or may be learned with the practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
To achieve the advantages and novel features, the present invention is generally directed to a system and method for testing component tolerances of a device for testing integrated circuits, the device having a plurality of test connectors disposed at a test head, each test connector having electrical conductors carrying electrical signals for a test channel, wherein each test channel corresponds to a circuit board that includes at least one driver and one receiver. In accordance with the broad concepts and teachings of the invention, an apparatus and method operate to compare driver and receiver components by interconnecting drivers from a first board to receivers of a second board, and vice-versa. Since built in test procedures provided by the tester manufacturer typically calibrate the drivers and receivers of a single pin, using cables and relays to hook that single pin to all other pins in the system, one at a time. Accordingly, the cross-check provided by the present invention provides a much improved system and method for verifying the accuracy of the operation of tester components.
In accordance with one aspect of the invention, an apparatus is provided for testing component tolerance of a device for testing integrated circuits. The testing device is generally characterized by a plurality of test connectors disposed at a test head, wherein each test connector carries electrical signals for a test channel. Further,
Armstrong David H.
Lawrence William R.
Agilent Technologie,s Inc.
Cady Albert De
Ramarre Guy
LandOfFree
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