Error detection/correction and fault detection/recovery – Pulse or data error handling – Replacement of memory spare location – portion – or segment
Reexamination Certificate
2006-08-01
2006-08-01
Ton, David (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Replacement of memory spare location, portion, or segment
C714S718000, C714S733000
Reexamination Certificate
active
07085972
ABSTRACT:
System for testing a group of functionally independent memories (102) and for replacing failing memory words of the group of functionally independent memories (102) by redundant memory words, comprising: redundancy means108) including at least one array of redundant memory words (108a) and address registers (108b) connected to at least one array of redundant memory words (108a); a test means (114); a group of first multiplexers (110) following the test means (114) and preceding the memories (102) and the at least one array of redundant memory words (108a); and a group of second multiplexers (112) following the memories (102) and the at least one array of redundant memory words (108a), wherein each second multiplexer (112) is connectable to the test means (114).
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Borri Simone
Kirmser Stephane
Infineon - Technologies AG
Jenkins Wilson Taylor & Hunt, P.A.
Ton David
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