System for test data storage reduction

Details System for test data storage reduction System for test data storage reduction

1993-08-04

2000-03-21

Le, Dieu-Minh T.

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

714726, G06F 1100

Patent

active

060414294

ABSTRACT:
A seed skipping mechanism is provided for use in conjunction with a linear feedback shift register used as a pseudo-random pattern generator for generating sequences of test bit streams for testing integrated circuit devices. The utilization of seed skipping for the pseudo-random pattern number generator in connection with weighting of the patterns from the random pattern generator provides an effective and low cost solution to data storage problems associated with generating effective test patterns for testing integrated circuit chip devices.

REFERENCES:
patent: 4513418 (1985-04-01), Bardell
patent: 4519078 (1985-05-01), Komonytsky
patent: 4715034 (1987-12-01), Jacobson
patent: 4801870 (1989-01-01), Eichelberger
patent: 4903266 (1990-02-01), Hack
patent: 5029171 (1991-07-01), Lee
patent: 5175494 (1992-12-01), Yoshimori
patent: 5257268 (1993-10-01), Agrawal
International Test Conference 1940, IEEE, pp. 657-659 "Multiple Seed Linear Feedback Shift Register"by J. Saver, et al.
International Test Conference--1989-pp. 264-274, IEEE, "Hardware-Base Weighted Random Pattern Generation for Boundary Scan" by C. Gloster.
FTCS 16th Annual Inter Symposium, IEEE, pp. 404-409 "Pseudaex hausitive Test Pattern Generator with Enhanced Fault Coverage" by P. Golan et al.

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