System for testing an integrated circuit using multiple test...

Details System for testing an integrated circuit using multiple test... System for testing an integrated circuit using multiple test...

2007-01-16

2007-01-16

Lamarre, Guy (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital logic testing

C714S036000, C714S731000

Reexamination Certificate

active

10196338

ABSTRACT:
A system for testing an integrated circuit at a plurality of locations with a plurality of test modes includes a sequence of test-mode storage devices, each of which has an input and an output. The sequence includes at least first and second test-mode storage devices located at corresponding first and second locations on the integrated circuit and configured to store first and second test modes. The first test-mode storage device is configured to perform a shift operation by providing the first test-mode at its output. The second test-mode storage device has its input connected to the output of the first test-mode storage device. This second device is configured to perform the shift operation by receiving, at its input, the first test mode and providing, at its output, the second test-mode.

REFERENCES:
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IEEE Std 1149.1-1990,IEEE Standard Test Access Port and Boundary—Scan Architecture,Feb. 15, 1990.

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