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Reconfiguration device for faulty memory

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate

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Recording medium having spare area for defect management and...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Recording medium structure capable of displaying defect rate

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Recording test information to identify memory cell errors

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Recovery while programming non-volatile memory (NVM)

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Reduced signal test for dynamic random access memory

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Redundancy correction ROM

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Redundancy method and circuit for self-repairing memory arrays

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Patent

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Register file and its storage device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Reliability monitor for a memory array

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Relocating unreliable disk sectors when encountering disk...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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ROM testing circuit

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Patent

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ROM-based controller monitor in a memory device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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ROM-based controller monitor in a memory device

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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RRAM controller built in self test memory

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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RRAM controller built in self test memory

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Runtime programmable BIST for testing a multi-port memory...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Scanned memory testing of multi-port memory arrays

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Scanning reassigned data storage locations

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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Scheme for the reduction of extra standby current induced by...

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
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