Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Patent
1996-10-31
1999-10-19
Beausoliel, Jr., Robert W.
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
365201, G01R 3128
Patent
active
059681900
ABSTRACT:
The present invention concerns a circuit and method to automatically test and disable defective rows in a FIFO or other buffer where the wordlines or rows of the FIFO buffer are driven by a shift register scheme. Additional enabled rows may be placed within the normal memory array. The additional enabled rows are substituted, as needed, for one or more defective rows. As a result, a defective row can be automatically disabled without effecting the operation of the FIFO, particularly the read or write data path. In one example, the disabling effect is achieved by using a comparison circuit to determine if the words read from the memory are accurate. The present invention can be used to effectively bypass any single shift register element or a multiple number of shift register elements.
REFERENCES:
patent: 4615030 (1986-09-01), Kumagai
patent: 4802122 (1989-01-01), Auvinen et al.
patent: 4839866 (1989-06-01), Ward et al.
patent: 4875196 (1989-10-01), Spaderna et al.
patent: 4891788 (1990-01-01), Kreifels
patent: 5084837 (1992-01-01), Matsumoto et al.
patent: 5088061 (1992-02-01), Golnabi et al.
patent: 5228002 (1993-07-01), Huang
patent: 5241501 (1993-08-01), Tanaka
patent: 5262996 (1993-11-01), Shiue
patent: 5278793 (1994-01-01), Yeh
patent: 5305253 (1994-04-01), Ward
patent: 5311475 (1994-05-01), Huang
patent: 5317756 (1994-05-01), Komatsu et al.
patent: 5367486 (1994-11-01), Mori et al.
patent: 5404332 (1995-04-01), Sato et al.
patent: 5406273 (1995-04-01), Nishida et al.
patent: 5406554 (1995-04-01), Parry
patent: 5416740 (1995-05-01), Fujita et al.
patent: 5426612 (1995-06-01), Ichige et al.
patent: 5459733 (1995-10-01), Alapat
patent: 5467319 (1995-11-01), Nusinov et al.
patent: 5479370 (1995-12-01), Furuyama et al.
patent: 5487041 (1996-01-01), Wada
patent: 5490257 (1996-02-01), Hoberman et al.
patent: 5506809 (1996-04-01), Csoppenszky
patent: 5513318 (1996-04-01), van de Goor et al.
patent: 5521876 (1996-05-01), Hattori et al.
patent: 5546347 (1996-08-01), Ko et al.
patent: 5619461 (1997-04-01), Roohparvar
patent: 5642318 (1997-06-01), Knaack et al.
patent: 5652725 (1997-07-01), Suma et al.
Beausoliel, Jr. Robert W.
Cypress Semiconductor Corp.
Iqbac Nadeem
Maiorana P.C. Christopher P.
LandOfFree
Redundancy method and circuit for self-repairing memory arrays does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Redundancy method and circuit for self-repairing memory arrays, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Redundancy method and circuit for self-repairing memory arrays will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2050293