Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
1998-05-20
2001-01-16
Moise, Emmanuel L. (Department: 2784)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
C714S711000, C714S725000, C365S200000, C365S201000, C365S227000, C365S229000, C326S013000, C326S014000
Reexamination Certificate
active
06175938
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a repairing method, more specifically, to a repairing scheme for the reduction of extra standby current induced by process defects.
2. Description of the Related Art
As the portable electronic products such as notebook computers, cellular phone, and personal digital agency (PDA) are widely used, the demands of static random access memory (SRAM) are also increasing. In order to prolong the life of the battery used by the portable electronic products, generally the integrated circuits (ICs) must meet the requirement for low power consumption. To achieve the object, the ICs are designed to have a small standby current, thereby reducing the unnecessary power consumption.
FIG. 1
illustrates the structure of a conventional SRAM. In
FIG. 1
, C
1
, C
2
~Cn represent the memory cells of SRAM; WL
1
, WL
2
~WLn represent the word lines; BL, BLB are bit lines (bit-line and bit-line bar); and Q
1
, Q
2
are pull-up transistors which are always kept in an on state. The bit lines BL and BLB may be shorted to the ground (for example Vss) due to the process defects such as metal defects, etc. Although using redundancy can repair those defects, there are still some problems. Since the pull-up transistors in a cell are always on, therefore a leakage current (about 1~2 mA in general) may flow through bit lines to the ground, even if other defects are repaired. The leakage currents may not influence the logic function of SRAM, however, the SRAM will consume a great amount of power even in a standby state. So the SRAM will be picked out in a standby current test. A minority of the above current defects will induce a total standby current over the specification, and the whole chip will be discarded, even though the logic function of SRAM is correct. Consequently, the yield is reduced, and the cost is raised.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a scheme for reduction of extra standby current induced by process defects. According to the present invention, after the bit lines and cells, with failure due to process defects, are repaired by using redundancy in a repairing process, the fuses connected with the pull-transistors coupled to the defect bit lines are disconnected, therefore cutting the leakage current completely.
Another object of the present invention is to reduce the standby leakage current such that the SRAM can pass the standby current test and the yield is improved.
The present invention achieves the above-indicated objects by providing a scheme for the reduction of extra standby current induced by process defects as described as follows, wherein every one of the pull-up transistors of the memory cells is connected with a fuse.
The test scheme starts to test the memory cells in a SRAM chip of a wafer to identify the addresses and locations of defect bit lines.
Next, test the other chips of the wafer in a lot and store the failure information data for repairing process.
Test the other wafers of the lot and store the failure information data for repairing process.
Then the repairing process is carried out by using redundancy to repair the defects of chips according to the failure information data, wherein the fuses connected with said pull-transistors corresponding to said defect bit lines are disconnected while finishing repairing.
Finally, the chips are tested again for proper verification of repairing.
The above steps of the test scheme takes the lot as a test unit, while the scheme can take a whole wafer as a test unit, and the steps are described as follows.
(a) The test scheme starts to test the memory cells in a SRAM chip to identify the addresses and locations of defective bit lines.
(b) Step (a) is repeated to test the chips of the whole wafer and storing the failure information data for a repairing process.
(c) The defects of chips are repaired in the repairing process by using redundancy according to the failure information data, wherein the fuses connected with said pull-transistors corresponding to said defective bit lines are disconnected while finishing the repairing process.
(d) Next, the chips are tested again for proper verification of repairing.
(e) Finally, step (a) to step (d) are carried out for testing and repairing other wafers.
REFERENCES:
patent: 4228528 (1980-10-01), Cenker et al.
patent: 4713814 (1987-12-01), Andrusch et al.
patent: 4761767 (1988-08-01), Ferrant
patent: 5111073 (1992-05-01), Suzuki et al.
patent: 5262993 (1993-11-01), Horiguchi et al.
patent: 5289475 (1994-02-01), Slemmer
patent: 5410510 (1995-04-01), Smith et al.
patent: 5677917 (1997-10-01), Wheelus et al.
Birch & Stewart Kolasch & Birch, LLP
Moise Emmanuel L.
Winbond Electronics Corp.
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