Reconfiguration device for faulty memory

Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing

Reexamination Certificate

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C714S042000, C714S724000

Reexamination Certificate

active

07073102

ABSTRACT:
A device for reconfiguring faults in a circuit comprised of several units and comprising storage means for storing the fault locations, connection/disconnection means for disconnecting faulty units and connecting in their place fault-free units, and means for generating control signals of the connection/disconnection means, responding to the content of the storage means. According to this method, each unit is divided into several portions; in a test phase, fault tests are carried out for the different units, and the test results of the different portions of the units are stored in the storage means; and in a use phase aiming at the use of given unit portions, said control signals are determined by the content of the storage means corresponding to these unit portions.

REFERENCES:
patent: 5293348 (1994-03-01), Abe
patent: 5303192 (1994-04-01), Baba
patent: 5781717 (1998-07-01), Wu et al.
patent: 6085334 (2000-07-01), Giles et al.
patent: 6327680 (2001-12-01), Gervais et al.
patent: 6345373 (2002-02-01), Chakradhar et al.
patent: 6829736 (2004-12-01), Marinissen et al.
patent: 2002/0141260 (2002-10-01), Wu et al.
patent: WO 01/16955 (2001-03-01), None

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