Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2011-05-17
2011-05-17
Kerveros, James C (Department: 2117)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
Reexamination Certificate
active
07945825
ABSTRACT:
Disclosed are methods and circuits for performing recovery associated with programming of non-volatile memory (NVM) array cells. According to embodiments, there are provided methods and circuits for programming NVM cells, including: (1) erasing NVM array cells; (2) loading an SRAM with user data; (3) if programming is successful, then flipping bits in the SRAM; and (4) if programming is not successful, reading data back from the array to the SRAM.
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Flash Memory Trends & Perspectives, Geoffrey MacGillivray, Semiconductor Insights. 2006 Flash Memory Summit.
Cohen Itzic
Danon Kobi
Hadas Shmulik
Tirosh Ori
Ettan Mehulal Law Group
Kerveros James C
Spansion Isreal, Ltd
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