Error detection/correction and fault detection/recovery – Pulse or data error handling – Memory testing
Reexamination Certificate
2000-12-07
2004-01-27
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Memory testing
Reexamination Certificate
active
06684353
ABSTRACT:
BACKGROUND
A memory cell may be a flash memory cell made of field effect transistors (FETs) that each include a select gate, a floating gate, a drain, and a source. Each memory cell may be read by grounding the source, and applying a voltage to a bitline connected with the drain. By applying a voltage to the wordline connected to the select gate, the cell can be switched “on” and “off.” Each memory cell in an array of memory cells store a “1” or a “0. ” Multi-level cells can store more than a single bit of data.
Programming a cell includes trapping excess electrons in the floating gate to increase the voltage. This reduces the current conducted by the memory cell when the select voltage is applied to the select gate. The memory cell is programmed when the cell current is less than a reference current and the select voltage is applied. The cell is erased when the cell current is greater than the reference current and the select voltage is applied.
A memory array may include multiple pages that are individually accessible. For example, a memory array may contain 64 pages and each page may contain 1 KB of memory cells. Each memory cell may be accessed by making the page that contains the memory cell the active memory page, then accessing the memory cell by selecting the row and column in the memory page that corresponds to the memory cell. The latency of making a memory page active is generally much larger than the access time of a memory cell. For example the page latency may be 3 microseconds while the cell access time may be only 50 nanoseconds.
A error may occur in a memory cell due to internal defects, normal use over a long period of time, non-use for a long period of time, or other factors. Two of the primary data reliability issues for memory cells are the “data retention” effect and “read disturb” effect. The “data retention” effect is a shift in the stored voltage level toward the erase state that results from the normal passage of time. The “read disturb” effect is a shift in the stored voltage level that results from reading the memory cell. For the read disturb effect to be appreciable, many reads must occur. When the stored voltage level shifts too far in either direction, it will be interpreted as representing the next higher or lower voltage level and thus the data will be misread.
An error checking and correction (ECC) circuit detects and optionally corrects errors in a memory array. An ECC circuit typically partitions a memory page into groups of memory cells and checks each group of memory cells independently and then generates a syndrome that indicates which memory cells had errors in each group. For example, a page of memory with 1 KB of memory cells may have 64 groups each containing 16 bytes of memory cells. Based on the algorithm of the ECC circuit and the size of the group, the memory cells in the group can be corrected if the total number of errors in the group is below a threshold. An ECC circuit typically generates a syndrome for each group that indicates which memory cells have errors. A syndrome that contains all zeros indicates that no errors were detected. If the number of errors in a group exceeds the threshold, none of the errors can be repaired. For example, the maximum number of errors that can be corrected in a memory array may be:
Max # of errors
= # of pages * # of groups * bits/group
Eqn. 1
Where:
Max # of errors
is the maximum number of errors that can be
corrected in the memory array.
# of pages
is the number of pages in the memory array.
# of groups
is the number of groups per page.
bits/group
is the number of bits that can be repaired per
group.
For the above example:
Max # of errors
= 64 * 64 * 16
Eqn. 2
= 1KB
The reliability of a memory array is dependent on many factors, some of which are process-dependent. Therefore, it is desirable to periodically test memory arrays to ensure that the manufacturing processes is functioning properly. Currently, complex and expensive test equipment must be connected with the memory array to test the reliability of the memory array. Also, the external test equipment typically cause delays during testing. These delays significantly lengthen the testing period for tests such as “read disturb” tests.
BRIEF SUMMARY
An integrated reliability monitor automatically tests a memory device until a threshold number of errors are detected. The integrated reliability monitor eliminates the need for sophisticated external test equipment by automatically testing the memory cells in the memory array and providing the results. Optional programmable registers may store the error threshold value. The programmable registers may also store a time-out value or the reliability monitor may be externally interrupted.
REFERENCES:
patent: 4748627 (1988-05-01), Ohsawa
patent: 5233614 (1993-08-01), Singh
patent: 5289475 (1994-02-01), Slemmer
patent: 5434868 (1995-07-01), Aichelmann, Jr. et al.
patent: 5909334 (1999-06-01), Barr et al.
patent: 5917766 (1999-06-01), Tsuji et al.
patent: 5933381 (1999-08-01), Iwata
patent: 5996105 (1999-11-01), Zook
patent: 6009547 (1999-12-01), Jaquette et al.
patent: 6021477 (2000-02-01), Mann
patent: 6052815 (2000-04-01), Zook
patent: 6079044 (2000-06-01), Cunningham et al.
patent: 6339546 (2002-01-01), Katayama et al.
Parker Allan
Skrovan Joseph
Advanced Micro Devices , Inc.
Chase Shelly A
De'cady Albert
LandOfFree
Reliability monitor for a memory array does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Reliability monitor for a memory array, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Reliability monitor for a memory array will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3252705