SR-flip flop with level shift function
SSTL voltage translator with dynamic biasing
Stacked buffers
Staged predriver for high speed differential transmitter
Staggered I/O groups for integrated circuits
Staggered output circuit for noise reduction
State machine and system and method of implementing a state...
State machine in a programmable logic device
State machines using non-volatile re-writeable two-terminal...
State machines using resistivity-sensitive memories
State saving and restoration in reprogrammable FPGAs
State splitting for level reduction
Static combinatorial logic circuits for reversible computation
Static current testing apparatus and method for current steering
Static logic circuit with improved output signal levels
Static logic compatible multiport latch
Static logic design for CMOS
Static memory cell circuit with single bit line and...
Static pulsed cross-coupled level shifter and method therefor
Static storage element for dynamic logic