Staggered output circuit for noise reduction

Details Staggered output circuit for noise reduction Staggered output circuit for noise reduction

1992-06-10

1994-11-08

Westin, Edward P.

Electronic digital logic circuitry

Signal sensitivity or transmission integrity

Output switching noise reduction

326 57, 327384, H03K 1716, H03K 513

Patent

active

053629965

ABSTRACT:
A method of reducing voltage spikes on voltage supply lines of an integrated circuit having a plurality of data signal lines each coupled to a tristate output buffer. The voltage spikes are reduced by enabling and disabling output buffers one at a time such that no two buffers become enabled or disabled simultaneously and by providing a different prespecified delay to each of the plurality of data signal lines so that no two output buffers are toggled simultaneously.

REFERENCES:
patent: 4616142 (1986-10-01), Upadhyay et al.
patent: 4820942 (1989-04-01), Chan
patent: 4857765 (1989-08-01), Cahill
patent: 5136185 (1992-08-01), Fleming et al.
patent: 5196743 (1993-03-01), Brooks

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