Flexible synchronous/asynchronous cell structure for a high dens
Flexible synchronous/asynchronous cell structure for a high dens
Flexible, high-performance static RAM architecture for field-pro
Flip flop with reduced leakage current
Flip-flop circuit
Flip-flop for use in LSSD gate arrays
Floor plan for scalable multiple level tab oriented...
Floor plan for scalable multiple level tab oriented...
Floor plan for scalable multiple level tab oriented...
Floor planning for programmable gate array having embedded...
Formation of columnar application specific circuitry using a...
Four state programmable interconnect device for bus line and...
FPGA and embedded circuitry initialization and processing
FPGA architecture at conventional and submicron scales
FPGA architecture based on a single configurable logic module
FPGA architecture having RAM blocks with programmable word lengt
FPGA architecture having two-level cluster input...
FPGA architecture having two-level cluster input...
FPGA Architecture using multiplexers that incorporate a logic ga
FPGA architecture with deep look-up table RAMs