Electronic digital logic circuitry – Multifunctional or programmable
Reexamination Certificate
2001-06-01
2003-04-08
Lee, Michael G. (Department: 2876)
Electronic digital logic circuitry
Multifunctional or programmable
C326S038000, C326S039000, C326S041000, C326S044000, C365S185330, C365S185290
Reexamination Certificate
active
06545504
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is related to programmable switches for integrated circuits, such as configurable system-on-chip circuits, field programmable gate arrays and other devices using programmable switches for interconnecting circuit elements.
2. Description of Related Art
Programmable switches are used in a wide variety circuit devices in order to increase the flexibility of designs. For example, a field programmable gate array includes an array of logic elements and wiring interconnections with thousands of programmable interconnects which are implemented using switches that are programmable in the field. Each programmable switch can connect or disconnect circuit elements, such as nodes in two logic circuits and such as wiring interconnections between modules in the circuit.
In addition to field programmable gate array devices, programmable switches and other programmable logic are being applied for so-called system-on-chip designs, which typically include a processor module, a non-volatile memory module, and a programmable logic module among other components. The programmable switches may be used for interconnect structures inside such circuit modules, or between such circuit modules.
It has been proposed to use charge programmable non-volatile memory elements for programmable switches. See U.S. Pat. No. 5,247,478, U.S. Pat. No. 5,764,096 and U.S. Pat. No. 6,122,209. In these patents, floating gate memory cells are used in combination with complex circuitry for programming and erasing such cells. The source and drain of the floating gate memory cell in such switches are coupled to the nodes to be connected or disconnected. The floating gate which controls the operation of the switch is then coupled to independent lines that are used for injecting for removing charge to set the state of the switch. These prior art approaches are relatively large and complex for use as programmable switches in high density integrated circuit environments.
As the uses of programmable switches are expanding, and the density and complexity of the integrated circuits using such switches increases, it is important that the area and the complexity of such switches is reduced. Furthermore, it is desirable that such switches are able to interconnect the circuit elements without significant degradation in voltage across the switch.
SUMMARY OF THE INVENTION
The present invention provides a one transistor, non-volatile programmable switch having four operating states for connection between circuit elements and passive elements including bus lines and input/output pads. The four states include including a first unidirectional state in which the cell allows signal flow in a first direction, as second unidirectional state in which the cell allows signal flow in a second direction, opposite to the first direction, a third state in which the cell allows bi-directional signal flow, and a fourth state presenting high impedance in which signal flow is blocked (the switch is open).
The programmable switch according to the present invention is used in an integrated circuit, and comprises a first node and a second node coupled with corresponding circuit elements in the integrated circuit. A non-volatile programmable transistor having a drain coupled to one of the first node and second node, a source coupled to the other of the first node and second node, gate coupled to an energizing conductor, and a data storage structure constitute the programmable switch.
In one embodiment, the non-volatile programmable transistor used in the switch is a charge programmable device (e.g. SONOS cell, see U.S. Pat. No. 6,011,725 for a description of such SONOS cells), in which the data storage structure comprises a nitride layer, or other charge trapping layer, between oxides or other insulators.
In one embodiment, a charge pump is coupled to the energizing conductor to produce a boosted voltage during logical operation of integrated circuit. The boosted voltage in one preferred embodiment comprises a voltage greater than the power potential on said circuit element by at least a threshold voltage of the programmable transistor, so that voltage dissipation across the programmable switch is minimized or eliminated.
In yet another embodiment, in which the non-volatile programmable transistor is a charge programmable device, programmable circuitry is coupled to the first and second nodes, and to the energizing conductor to apply voltages sufficient to inject and remove charge from the charge storage structure for programming the charge programmable device.
For integrated circuits in which voltages used for programming and erasing the non-volatile charge programmable device are high relative to the design rule for the circuit elements to be interconnected, a structure coupled with the circuit elements to withstand the high voltages is included. In one embodiment, the circuit element coupled with the first node comprises a transistor, and the structure to withstand the high voltages applied by the programming circuitry comprises a gate insulator adapted to withstand the voltages. In one embodiment, the gate insulator comprises essentially silicon dioxide having a thickness sufficient to withstand the voltages.
In one embodiment, the programming circuitry includes logic to disconnect power from the circuit element coupled to the second node while applying energy to inject or remove charged from the charge storage element. Another embodiment, the programming circuitry includes a first voltage conductor coupled to the first node, a second voltage conductor to the second node, and logic to disconnect the first and second voltage conductors from the first and second nodes during logical operation of the integrated circuit.
Other aspects and advantages of the present invention can be seen upon review of the figures, the detailed description and the claims which follow.
REFERENCES:
patent: 4870470 (1989-09-01), Bass, Jr. et al.
patent: 4871930 (1989-10-01), Wong et al.
patent: 4879688 (1989-11-01), Turner et al.
patent: 5015885 (1991-05-01), Gamal et al.
patent: 5028810 (1991-07-01), Castro et al.
patent: 5042004 (1991-08-01), Agrawal et al.
patent: 5117389 (1992-05-01), Yiu
patent: 5227335 (1993-07-01), Holschwandner et al.
patent: 5247478 (1993-09-01), Gupta et al.
patent: 5251169 (1993-10-01), Josephson
patent: 5260610 (1993-11-01), Pedersen et al.
patent: 5317534 (1994-05-01), Choi et al.
patent: 5341337 (1994-08-01), Hotta
patent: 5392233 (1995-02-01), Iwase
patent: 5559733 (1996-09-01), McMillan et al.
patent: 5625586 (1997-04-01), Yamasaki et al.
patent: 5640344 (1997-06-01), Pani et al.
patent: 5731608 (1998-03-01), Hsu et al.
patent: 5739569 (1998-04-01), Chen
patent: 5761120 (1998-06-01), Peng et al.
patent: 5764096 (1998-06-01), Lipp et al.
patent: 5768192 (1998-06-01), Eitan
patent: 5821581 (1998-10-01), Kaya et al.
patent: 5901330 (1999-05-01), Sun et al.
patent: 5905674 (1999-05-01), Choi
patent: 5943259 (1999-08-01), Choi
patent: 5944593 (1999-08-01), Chiu et al.
patent: 5949710 (1999-09-01), Pass et al.
patent: 5995744 (1999-11-01), Guccione
patent: 6011725 (2000-01-01), Eitan
patent: 6023102 (2000-02-01), Nguyen et al.
patent: 6028445 (2000-02-01), Lawman
patent: 6049222 (2000-04-01), Lawman
patent: 6094065 (2000-07-01), Tavana et al.
patent: 6102963 (2000-08-01), Agrawal
patent: 6105105 (2000-08-01), Trimberger
patent: 6122209 (2000-09-01), Pass et al.
patent: 6181597 (2001-01-01), Nachumovsky
patent: 6272655 (2001-08-01), Hecht et al.
patent: 6295230 (2001-09-01), Madurawe et al.
patent: 6323671 (2001-11-01), Ra
patent: 6331463 (2001-12-01), Chen
John Villasenor et al. “Configurable Computing” Scientific American Configurable Computing Jun. 1997 pp. 1-10.
“IBM to Fab Xilinx Ics, Moves Copper 0.13-/0.10-micron Processes to Foundry Services” Semiconductor Business News—Silicon Strategies consisting of two pages dated Mar. 4, 2002.
“IBM, Xilinx to Put PowerPC Core In FPGAs; Foundry Deal Includes Copper Processes” Semiconductor Business News—Silicon Strategies consisting o
Lo Ying-Che
Sheu Eric
Sun Albert
Haynes Mark A.
Haynes Beffel & Wolfeld LLP
Lee Michael G.
Macronix International Co. Ltd.
Paik Steven S.
LandOfFree
Four state programmable interconnect device for bus line and... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Four state programmable interconnect device for bus line and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Four state programmable interconnect device for bus line and... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3069738