Safety system based on reconfigurable array of logic gates

Sample and load scheme for observability of internal nodes in a

Scalable architecture for high density CPLD's having...

Scalable architecture for high density CPLDS having...

Scalable complex programmable logic device with segmented...

Scalable device architecture for high-speed interfaces

Scalable multiple level tab oriented interconnect architecture

Scalable non-blocking switching network for programmable logic

Scalable non-blocking switching network for programmable logic

Scalable non-blocking switching network for programmable logic

Scalable non-blocking switching network for programmable logic

Scalable non-blocking switching network for programmable logic

Scalable serializer-deserializer architecture and...

Scalable shared network memory switch for an FPGA

Scaleable padframe interface circuit for FPGA yielding improved

Scan flip-flop circuit, scan flip-flop circuit array, and...

SCL type FPGA with multi-threshold transistors and method...

SCSI cable with two cable segments having a first resistor coupl

SCSI controller having output driver with slew rate control

Segmented configuration of programmable logic devices