FPGA architecture having two-level cluster input...

Details FPGA architecture having two-level cluster input... FPGA architecture having two-level cluster input...

2007-09-14

2008-08-05

Tran, Anh Q (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S039000, C326S047000

Reexamination Certificate

active

07408383

ABSTRACT:
An interconnect architecture for a programmable logic device comprises a plurality of interconnect routing lines. The data inputs of a plurality of first-level multiplexers are connected to the plurality of interconnect routing lines such that each interconnect routing line is connected to only one multiplexer. A plurality of second-level multiplexers are organized into multiplexer groups. Each of a plurality of lookup tables is associated with one of the multiplexer groups and has a plurality of lookup table inputs. Each lookup table input is coupled to the output of a different one of the second-level multiplexers in the one of the multiplexer groups with which it is associated. The data inputs of the second-level multiplexers are connected to the outputs of the first-level multiplexers such that each output of each first-level multiplexer is connected to an input of only one second-level multiplexer in each multiplexer group.

REFERENCES:
patent: 6292019 (2001-09-01), New et al.
patent: 6556042 (2003-04-01), Kaviani
Betz, Vaughn et al., “Cluster-Based Logic Blocks” , Chapter 6, in Architecture and CAD for Deep-Submicron FPGAs, 1999, second printing 2000, pp. 137-141, Kluwer Academic Publishers, Norwell, MA, USA, no month.
Feng, Wenyi et al., “Designing Efficient Input Interconnect Block for LUT Clusters Using Counting and Entropy”, Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field-programmable gate arrays, Feb. 20-22, 2007 held in Monterey, CA, pp. 23-32, ACM, New York, NY USA.
Lemieux, Guy, “Sparse Crossbar Design”, Chapter 4, in Design of Interconnection Networks for Programmable Logic, 2004, pp. 77-79, Kluwer Academic Publishers, Norwell, MA, USA, no month.
Lewis, David et al., “The Stratix II Logic and Routing Architecture”, Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays, Feb. 20-22, 2005 held in Monterey, CA, pp. 14-20, ACM, New York, NY, USA.

Affiliated with

Also associated with

Rating

FPGA architecture having two-level cluster input... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with FPGA architecture having two-level cluster input..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and FPGA architecture having two-level cluster input... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4018795