Data bus circuit and method of changing over termination resisto

Data bus controller having a level setting circuit

Data driver systems with programmable modes

Data input/output circuit included in semiconductor memory...

Data latch with low-power bypass mode

Data latch with low-power bypass mode

Data latch with structural hold

Data monitoring for single event upset in a programmable...

Data path configurable for multiple clocking arrangements

Data processing system with improved latency and associated...

Data transfer control circuitry including FIFO buffers

Data transfer on reconfigurable chip

Data-driven clock gating for a sequential data-capture device

Data-driven clock gating for a sequential data-capture device

Datapath global routing using flexible pins for side exiting...

Decision-feedback equalization clocking apparatus and method

Decoder structure and method for FPGA configuration

Dedicated crossbar and barrel shifter block on programmable...

Dedicated crossbar and barrel shifter block on programmable...

Dedicated crossbar and barrel shifter block on programmable...