Gatable level-pulling circuit
Gate array base cell with multiple P-channel transistors
Gate array cell with predefined connection patterns
Gate array cell with predefined connection patterns
Gate array cell with predefined connection patterns
Gate driving circuit and display apparatus having the same
Gating logic circuits in a self-timed integrated circuit
General purpose input/output system and method
General-purpose logic array and ASIC using the same
General-purpose logic cell, general-purpose logic cell array...
Gigabit router on a single programmable logic device
Global chip interconnect
Global signal distribution with reduced routing tracks in an FPG
GPIO mux/dynamic port configuration