Flip flop with reduced leakage current

Details Flip flop with reduced leakage current Flip flop with reduced leakage current

2002-09-27

2004-08-24

Cho, James H. (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Sequential or with flip-flop

C326S094000, C327S202000

Reexamination Certificate

active

06781411

ABSTRACT:

This application claims priority to European Application Serial No. 02290204.3, filed Jan. 29, 2002 (TI-31098EU).
CROSS-REFERENCES TO RELATED APPLICATIONS
Not Applicable.
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not Applicable.
BACKGROUND OF THE INVENTION
The present embodiments relate to electronic circuitry and are more particularly directed to a flip flop with reduced leakage current.
A clocked flip-flop utilizes sequential logic to selectively latch one of two binary states. a logic “0” or a logic “1”. A D flip-flop inputs a binary data input D and in response to clock transitions thereafter outputs D at a binary data output Q. Typical flip-flops of this type use a master and a slave section with the master section initially clocked on one level of a clock signal to store the logic state from input D on a master node, and then, on the next level of the clock, to transfer this logic state to a slave node for storage and also to output it on the Q output. In this manner, on the next clock cycle, another logic state can be stored on the master node without affecting the slave node.
By way of further background, U.S. Pat. No. 5,250,852 (hereafter, the '852 Patent) is entitled “Circuitry And Method For Latching A Logic State,” issued on Oct. 5, 1993, and is hereby incorporated herein by reference. The '852 Patent illustrates two alternative flip-flops (see FIGS. 1 and 2 thereof), with
FIG. 1
of the present application introducing the implementation of FIG. 1 in the '852 patent so as to further appreciate both the prior art and the preferred embodiments described below. Turning to
FIG. 1
, it illustrates an electrical block diagram of a prior art flip flop
10
. Flip flop
10
receives data D at a data input
12
to a master circuit
14
, and master circuit
14
also receives a clock signal {overscore (CLK)} at a clock input
16
. The use of {overscore (CLK)} rather than its complement (i.e., {overscore (CLK)}) is simply to maintain consistency with the '852 patent, where one skilled in the art will appreciate that comparable operation could be achieved based on a complementary clock signal using the appropriate connections and circuitry within flip flop
10
. The output of master circuit
14
is connected to master output node
18
, and master output node
18
is connected to a data input
19
of a slave circuit
22
. Slave circuit
22
also receives the clock signal {overscore (CLK)} at a clock input
24
. Returning to master output node
18
, it is also connected to a first input
20
1
of a multiplexer
20
. A second input
20
2
of multiplexer
20
is connected to a slave output node
26
. The output of multiplexer
20
provides the Q output of flip flop
10
, as further appreciated from the operational description provided below.
FIG. 2
illustrates a timing diagram of various signals in connection with the prior art flip flop
10
of
FIG. 1
, and the operation of flip flop
10
is now described in connection with those signals. In general, data D from input
12
is clocked through flip flop
10
and provided at the Q output. To illustrate this operation, assume data D at a time t
1
is represented by D
1
, and the following discussion traces the passage of D
1
through flip flop
10
. At t
1
, {overscore (CLK)} transitions from low to high, and this transition doses master circuit
14
, that is, a conductive path is closed through master circuit
14
to pass data D
1
from input
12
to master output node
18
. In this regard, master circuit
14
includes a transfer gate to perform this function and which is sometimes referred to with other terminology such as a passgate. Accordingly, after a certain delay associated with the devices of the conductive path through master circuit
14
, and thus at a time t
1.1
, D
1
is shown in
FIG. 2
to appear at master output node
18
. The state of D
1
is retained at master output node
18
, typically by way of a latch circuit within master circuit
14
. At T
2
, {overscore (CLK)} transitions from high to low, and this transition doses slave circuit
22
, that is, a conductive path is dosed through slave circuit
22
to pass data D
1
from its input
19
to slave output node
26
; similar to master circuit
14
, slave circuit
22
typically includes a transfer gate to achieve this function. Accordingly, after a certain delay associated with the devices of the conductive path through slave circuit
22
, and thus at a time t
2.2
, D
1
is shown in
FIG. 2
to appear at slave output node
26
, where D
1
is typically retained by way of a latching circuit included within slave circuit
22
. Notably, in addition to the closing of slave circuit
22
, the low level following the transition of {overscore (CLK)} at t
2
also causes multiplexer
20
to select the data at its input
20
1
, that is, multiplexer
20
selects the data from master output node
18
. As a result, at a time t
2.1
that follows a multiplexer delay, the Q output of flip flop
10
provides D
1
. As a noted benefit of this prior art approach, the multiplexer delay between t
2
and t
2.1
is shorter than the delay time between t
2
and T
2.2
as required for D
1
to pass through slave circuit
22
. In other words, the output of flip flop
10
is valid sooner due to the use of multiplexer
20
as compared to other prior art approaches that provide the Q output as an output solely from the slave circuit. Another manner of stating this is with respect to what is referred to in the flip flop art as the clock-to-Q time for the flip flop, that is, the time required between the slave-closing clock transition (e.g., t
2
) and the time the Q output is valid (i.e., t
2.1
). For flip flop
10
, this clock-to-Q parameter is shorter and, hence improved, as compared to the art that preceded the '852 patent.
To complete a discussion of one full clock period in
FIG. 2
, note that at time t
3
there is another low to high transition of {overscore (CLK)}. In response, master circuit
14
again closes to transfer the next data, D
2
, to master output node
18
; however, also in response to the high level after the transition of {overscore (CLK)}, multiplexer
20
switches to select its input
20
2
and provides it at the Q output. Thus, at the same time that master circuit
14
is transferring D
2
, D
1
is still available at slave output node
26
, and since that node is connected to input
20
2
of multiplexer
20
then at that time it is connected to the Q output. In other words, although the t
3
low to high transition of {overscore (CLK)} once again closes master circuit
14
, this does not affect the output of flip flop
10
because that output is then taken from slave output node
26
which remains unchanged in response to the t
3
{overscore (CLK)} transition.
While the approach of the '852 patent provides an improved flip flop device, the present inventors have observed that such an approach may be improved still further with respect to power consumption. Specifically, the electronics industry is increasingly focused on reduction of power consumption in electronic circuits. Power is generally consumed by a circuit during active operation and also due to leakage, where the latter relates to the various conductive paths that are not fully enabled at a given time but which are nonetheless leaking current and thereby consuming energy. Leakage power is presently still smaller than active power, but leakage power has become a comparable issue due to the increasing importance of battery-powered devices. As a result, there is a focus in the industry to reduce both types of power consumption, including leakage power loss. For example, in the area of circuits in general, one approach is to identify times when operation is unneeded, and to reduce the active state of the device during that time. This modified state is often referred to as a certain mode, and includes various names such as reduced power mode, sleep mode, and various other terms used in the art. With respect to a flip flop in such a state, one approach has been to shift

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