Flip-flop for use in LSSD gate arrays

Details Flip-flop for use in LSSD gate arrays Flip-flop for use in LSSD gate arrays

1994-09-13

1995-11-21

Westin, Edward P.

Electronic digital logic circuitry

Multifunctional or programmable

Sequential or with flip-flop

326 16, 327203, H03K 19173

Patent

active

054690790

ABSTRACT:
A flip-flop designed for use in gate arrays following LSSD design rules. The flip-flop has a data input D and a scan data input SD which are gated by control signals fmc, fmc' to the flip-flop input terminal 18. The flip-flop input 18 is gated into a master flip-flop consisting of two inverters 30, 32 coupled back-to-back by a gate signal DMC which is valid when the desired input signal is gated to the flip-flop input 18. The master flip-flop is coupled to a slave flip-flop which is gated by a different control signal. The slave flip-flop consists of two inverters 44, 46 coupled back-to-back. Inverters 48, 50 coupled to the slave flip-flop provide a buffered output therefrom.

REFERENCES:
patent: 5015875 (1991-05-01), Giles
patent: 5017809 (1991-05-01), Turner
patent: 5130568 (1992-07-01), Miller
patent: 5173626 (1992-12-01), Kudou
patent: 5175447 (1992-12-01), Kawasaki
patent: 5252917 (1993-10-01), Kadowaki
patent: 5281864 (1994-01-01), Hahn

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