Flip-flop circuit

Details Flip-flop circuit Flip-flop circuit

2006-06-30

2008-09-23

Barnie, Rexford (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Sequential or with flip-flop

C326S095000, C327S199000, C327S200000, C327S201000, C327S202000, C327S203000

Reexamination Certificate

active

07427875

ABSTRACT:
Signal delivery delay margin of a bypass flip-flop circuit is stabilized during high-frequency operation. An input controller for logically operating a bypass signal and a clock produces first and second output signals having different states depending on whether or not the bypass signal is activated. A latch circuit latches input data based on the first and second output signals. A latch controller logically operates the bypass signal and input data to generate a third output signal having a different state depending on whether or not the bypass signal is activated. An output controller is switched in response to the states of the first and second output signals for logically combining an output signal selected from the latch circuit and the third output signal to provide the output signal.

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Issue Date from the Korean Patent Office, Issued in Korean Patent Application No. 10-2005-0134193, dated on Jan. 17, 2007.

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