Data latch with structural hold

Details Data latch with structural hold Data latch with structural hold

2009-10-28

2010-11-30

Le, Don P (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Sequential or with flip-flop

C326S093000, C326S038000

Reexamination Certificate

active

07843218

ABSTRACT:
A multiplexed data flip-flop circuit (500) is described in which a multiplexer (510) outputs functional or scan data, a master latch (520) generates a master latch output signal at a hold time under control of a master clock signal, a slave latch (540) generates a flip flop output signal at a launch time under control of a slave clock signal, clock generation circuitry (550) generates a second clock signal that has a DC state during a functional mode and has a switching state during a scan mode, and data propagation logic circuitry (564) uses the first and second clock signals to generate the master and slave clock signals during a scan mode to delay the launch time of the slave latch with respect to the hold time of the master latch.

REFERENCES:
patent: 5920575 (1999-07-01), Gregor et al.
patent: 6389566 (2002-05-01), Wagner et al.
patent: 6895540 (2005-05-01), Chen et al.
patent: 7345519 (2008-03-01), Hirata
patent: 7436211 (2008-10-01), Ueda
patent: 7484149 (2009-01-01), Lackey
patent: 7596732 (2009-09-01), Branch et al.
patent: 2008/0012618 (2008-01-01), Ramaraju et al.
patent: 2008/0284480 (2008-11-01), Ahmadi

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