Data transfer control circuitry including FIFO buffers

Details Data transfer control circuitry including FIFO buffers Data transfer control circuitry including FIFO buffers

2005-04-26

2005-04-26

Wamsley, Patrick (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C370S235000, C375S372000

Reexamination Certificate

active

06885217

ABSTRACT:
Data transfer control circuitry includes a receive buffer for sequentially receiving received data, which are provided from a local processor together with a write control signal to store the data therein, and sequentially developing the stored data in response to a read control signal, which is provided from a host in the same order as stored. A transmit buffer sequentially receives data to be transmitted, which are provided from the host together with another write control signal, and sequentially develops the stored data in response to another read control signal provided from the local processor in the same order as stored. A counter increments a count in response to a clock signal and resets itself in response to either of the write control signals. A clock control circuit interrupts the clock signal when the count reaches a preset value.

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