Data-driven clock gating for a sequential data-capture device

Details Data-driven clock gating for a sequential data-capture device Data-driven clock gating for a sequential data-capture device

2006-04-04

2006-04-04

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S046000, C711S218000, C711S004000

Reexamination Certificate

active

07023240

ABSTRACT:
A circuit for capturing data from a bus having a flip-flop register, comparison logic and clock logic. The comparison logic determines whether any bit on the bus has changed logic state. If a bit has changed state, the comparison logic asserts an enable signal which causes the clock logic to clock the register. Accordingly, data from the bus is not clocked through the register unless the data has actually changed state and the comparison logic itself determines whether different data is present on the bus.

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patent: 6430697 (2002-08-01), Muljono
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patent: 6523136 (2003-02-01), Higashida
patent: 6842039 (2005-01-01), Guzman et al.

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