Data latch with low-power bypass mode

Details Data latch with low-power bypass mode Data latch with low-power bypass mode

2005-10-25

2005-10-25

Tran, Anh Q. (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S038000, C326S037000

Reexamination Certificate

active

06958624

ABSTRACT:
A bypassable latch circuit consumes less power in the bypass mode than it does in the latched mode. The circuit includes a flip-flop whose output is routed to an input of a multiplexer. The other input of the multiplexer is the input of the flip-flop as well. The multiplexer is used to select as the latch output either the registered or latched flip-flop output, or the flip-flop input. The flip-flop is modified by replacing the inverter at the flip-flop clock input with a logic gate that accepts as inputs both the clock input and a control input. The control input can cause the flip-flop to ignore the clock, preventing switching that consumes power by charging and discharging capacitive elements in the flip-flop.

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patent: 0 167 047 (1986-01-01), None
patent: WO95/16993 (1995-06-01), None

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