Data monitoring for single event upset in a programmable...

Details Data monitoring for single event upset in a programmable... Data monitoring for single event upset in a programmable...

2006-09-19

2006-09-19

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S041000, C326S113000, C365S230010, C365S189011

Reexamination Certificate

active

07109746

ABSTRACT:
Method and apparatus for data monitoring for error detection is described. A programmable logic device includes a configurable logic block having function generators, each of which is configurable for at least two programmable mode functions. The function generators are coupled to an array of memory cells for storing configuration bits for configuring the function generators. A primary address line is coupled to each memory cell spanning two or more of the function generators. A secondary address line is coupled to groups of memory cells associated with the function generators. A mask circuit is configured to selectively communicate a signal of the primary address line to a segment of the secondary address line or to a ground responsive in part to the program mode function.

REFERENCES:
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patent: 6242945 (2001-06-01), New
patent: 6822894 (2004-11-01), Costello et al.
U.S. Appl. No. 10/618,404, filed Jul. 11, 2003, Young.
U.S. Appl. No. 10/683,944, filed Oct. 10, 2003, Young.
U.S. Appl. No. 10/402,446, filed Mar. 27, 2003, Voogel et al.

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