Electronic digital logic circuitry – Multifunctional or programmable – Sequential or with flip-flop
Reexamination Certificate
2002-06-28
2004-11-23
Tan, Vibol (Department: 2819)
Electronic digital logic circuitry
Multifunctional or programmable
Sequential or with flip-flop
C326S093000, C326S095000, C327S199000, C327S144000, C327S225000, C327S230000
Reexamination Certificate
active
06822478
ABSTRACT:
STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT
Not applicable.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to capturing data on a multi-channel bus. More particularly, the invention relates to clock gating of sequential devices such as flip-flops or latches used to capture said data. More particularly still, the invention relates to a technique for enabling a clock signal to a sequential device upon detection of a change in the incoming data.
2. Background of the Invention
Modern semiconductor manufacturing technology makes it possible to produce integrated circuits (ICs) with complex circuits and millions of transistors on a single device. Discrete devices such as application specific integrated circuits (ASICs) perform a multitude of tasks and replace circuits that formerly required whole circuit card assemblies. Hence, the industry term “System on a Chip” (SOC) accurately reflects the ability to produce complex processing systems in a small amount of space. Microprocessors also generally reflect this miniaturization trend and include a variety of logic circuits fabricated on a single semiconductor chip. It is generally desirable for ICs such as processors to be compact, consume very little power, and generate as little heat as possible. This is especially true for processors that reside in small, battery-powered devices such as cellular telephones, pagers, and the like. However, as chip density continues to increase, heat dissipation and power reduction become more difficult to achieve.
One area of focus for reducing power consumption in ICs and microprocessor designs is clock signals. Clock signals are periodic signals that oscillate between high and low voltages many times per second. For example, a 500 MHz clock signals transitions from a high voltage to a low voltage and back to the high voltage (one clock cycle) 500 million times per second. In general, clock signals are used to trigger digital devices to perform a function. One common type of device that uses a clock signal is a “flip-flop.” A flip-flop receives an input data signal that may vary between two logic states (high and low). Upon detecting an edge (transition from low to high or high to low) of a clock input signal, the flip-flop samples and holds the state of the input data signal and causes the output signal of the flip-flop to transition to that state and remain at that state until the flip-flop is clocked again.
It is well known that routing a clock signal to many devices can cause significant energy losses due to the capacitive loading of the devices and of the signal paths themselves. Further, a flip-flop requires more power to actively sample and hold the input data signal upon being “clocked” than it requires in its idle state when the flip-flop is not being clocked. In a typical system, many flip-flops may be clocked by a single clock signal. Further, there may be numerous clock signals in a given system. Thus, when clock signals change state in a typical system, numerous flip-flops clock their input signals thereby causing an associated spike in power usage. This increase in power usage can be significant and also causes a rise in heat generation. Thus, it is desirable to reduce the load placed on clock sources. This can be accomplished by reducing the number of devices that must be clocked and/or by reducing the frequency with which clocked devices are switched.
FIGS. 1-3
show several conventional techniques for clocking flip-flops. In each Figure, flip-flop
10
is implemented as a “D-type” flip flop well known to those of ordinary skill in the art. In
FIG. 1
, flip-flop
10
is clocked every time the input clock signal (CLKin) changes from a low to a high logic level (i.e., every rising edge). A multiplexer
12
is also included which provides either the input data value (Din) or the previously captured value (Qout) to the flip-flop's D input. With this clocking scheme, flip-flop
10
is clocked on every rising edge of the CLKin signal regardless of whether the input data Din has actually changed or not. As such, the flip-flop
10
consumes power to latch data even if the data has not changed.
Using the multiplexer, the flip-flop
10
either clocks in the previously sampled data (Qout) or new data (Din) depending on the state of the enable signal (En). The enable signal (En) is typically generated by another device (not shown) that knows when the data, Din, has changed state. For example, in the case of a bus, the device that asserts the enable signal may be a bus master that changes the data and, at the same time, asserts the enable signal to tell the flip-flop that new data is ready to be captured. In the circuit shown in
FIG. 1
, because the enable signal and the data are asserted at the same time, this clocking method is called “synchronous load-enable clocking.”
The losses generated by constantly switching the flip-flops
10
in synchronous load-enable clocking schemes are reduced by implementing a gated clock circuit as shown in FIG.
2
. As shown, a logic gate
20
(e.g., an AND gate) is used to turn off the clock (CLKin) to flip-flop
10
when that device does not need to be clocked. With a gated clock, the enable signal (En) that controls the select line on the multiplexer
12
shown in
FIG. 1
now controls the AND gate
20
shown in FIG.
2
. Unless both the enable signal (En) and the clock signal (CLKin) are logically high, the gated clock signal (GCLK) will remain at a constant deasserted level and the flip-flop
10
will not clock the input data (Din). Disabling the clock signal in this manner saves on clock power since the local clock line (GCLK) to flip-flop
10
is not continuously toggling between high and low states. The advantage of this embodiment is particularly useful when the same clock signal is used to trigger multiple devices. By effectively turning off the clock signal to multiple devices, the capacitive load normally generated by those devices decreases considerably.
An unfortunate problem with the clock-gating example shown in
FIG. 2
is that the AND gate
20
may produce glitches or unintended spikes in the GCLK signal. This may occur, for example, when the enable signal falls after the input clock signal rises or, conversely, when the enable signal rises just before the input clock signal falls. In either case, it is possible, if both signals are high even for a small period of time, that a spike will appear in the GCLK signal. It is preferable that the GCLK signal that is, used to trigger the flip-flop
10
be uniform (i.e., each cycle in the clock signal be the substantially the same). Otherwise, the flip-flop
10
may spuriously latch the data or the setup and hold times for the flip-flop
10
may be violated. If the input data is not present for a required period of time before (setup) and after (hold) the input clock causes the flip-flop
10
to clock the data, then the data may not be reliable.
The third example shown in
FIG. 3
remedies this condition by providing a “latch”
30
as an input to the AND gate
20
to hold the enable signal (En) high at least through the end of the current clock cycle. A latch may be distinguished from a flip-flop by the way the devices trigger the data-capture feature. A latch is a clock level-sensitive device while a flip-flop is a clock edge-sensitive device. In other words, a latch will capture data if a clock signal driving the latch is high or low while a flip-flop captures data only on rising or falling clock edges. The latch
30
shown in
FIG. 3
captures input data when the input clock is low. Thus, if the enable signal is high during a low transition of the input clock, a high output will appear at the output (LQ) of the latch
30
. On the subsequent low to high transition of the input clock, the AND gate
20
will generate a high signal (GCLK) that remains high for at least half of a clock cycle and permits timely capturing of data as it arrives at flip-flop
10
.
A drawback to each of the conventional approaches discussed above is that
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