I/O architecture/cell design for programmable logic device

I/O block for a programmable interconnect circuit

I/O buffer architecture for programmable devices

I/O buffer circuit with pin multiplexing

I/O buffer circuit with pin multiplexing

I/O cell architecture for CPLDs

I/O circuitry shared between processor and programmable...

I/O circuitry shared between processor and programmable...

I/O circuitry shared between processor and programmable...

I/O transceiver having a pulsed latch receiver circuit

IC chip using a common multiplexor logic element for performing

IC with digital and analog circuits and mixed signal I/O pins

Implementation of high speed synchronous state machines with sho

Implementing complex clock designs in field programmable...

Implementing wide multiplexers in an FPGA using a horizontal...

In-line SCSI bus circuit for providing isolation and bi-directio

In-service programmable logic arrays with ultra thin...

In-system programmable interconnect circuit

In-system programming of a non-compliant device using...

In-system programming of a non-compliant device using...