Implementation of high speed synchronous state machines with sho

Details Implementation of high speed synchronous state machines with sho Implementation of high speed synchronous state machines with sho

1996-07-01

1998-10-27

Heckler, Thomas M.

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 46, H03K 19173, G06F 738

Patent

active

058288724

ABSTRACT:
An apparatus and method of handling short setup and hold time input signals. The apparatus separates the processing of the data signals into an input flip-flop portion, a state machine portion, a combinatorial logic mapping portion and a rapid selecting circuit. The input flip-flops capture the signals allowing processing when the hold times are very small. The state machine portion generates a new current state from the input signals. The combinatorial logic mapping circuit generates a set of possible outcomes based on the result of the state machine and moderate setup time inputs. A rapid selecting circuit quickly chooses among the possible outcomes based on received short setup and hold time signals.

REFERENCES:
patent: 4965472 (1990-10-01), Anderson
patent: 5389838 (1995-02-01), Orengo
patent: 5394557 (1995-02-01), Ellis
patent: 5644497 (1997-07-01), Hyman

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