I/O transceiver having a pulsed latch receiver circuit

Details I/O transceiver having a pulsed latch receiver circuit I/O transceiver having a pulsed latch receiver circuit

1993-11-12

1998-02-24

Louis-Jacques, Jacques H.

Electronic digital logic circuitry

Multifunctional or programmable

Array

326 80, 326 86, 326 93, 326115, 327 52, 327 96, 327287, 364488, G06F 300

Patent

active

057218757

ABSTRACT:
A GTL I/O transceiver circuit having a pulsed latch receiver. A pulse generator generates a first pulse and a second pulse within the first pulse in response to a rising edge of the bus clock. The first pulse turns on the differential amplifier of the receiver circuit just long enough to provide a valid amplifier output signal. The second pulse controls a tristate latch such that the value of the amplifier output signal is latched before the differential amplifier is turned off. The pulsed latch receiver turns the differential amplifier on for only a fraction of the period of the bus clock such that power dissipation of the pulsed latch receiver circuit is significantly reduced. By using the pulsed latch receiver in VLSI components having hundreds of I/Os, significant reduction in overall component power dissipation can be achieved and static DC power is eliminated. The GTL I/O transceiver is useful for interfacing VLSI CMOS components to a terminated bus.

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