Clock distributor for use in semiconductor logics for...
Clock generating apparatus for skew control between two-phase no
Clock skew reduction technique based on distributed process...
Clock synchronization of multiprocessor systems
Clocking an I/O buffer, having a selectable phase difference...
Clocking architecture to compensate a delay introduced by a...
Computer system having memory device with adjustable data...
Computer system having memory device with adjustable data...
Computer systems having apparatus for generating a delayed...
Configurage data setup/hold timing circuit with user...
Control of I.C.'s having different command protocols...
Converter circuit for synchronizing bus control signals...
Count calibration for synchronous data transfer between...
Count calibration for synchronous data transfer between...
Cyclemaster synchronization in a distributed bridge
Cyclemaster synchronization in a distributed bridge
Data bit-to-clock alignment circuit with first bit capture...
Data paths with receiver timing fixable to a downstream...
Data processing apparatus and method for translating a...
Data reception method