Clock skew reduction technique based on distributed process...

Details Clock skew reduction technique based on distributed process... Clock skew reduction technique based on distributed process...

2006-06-27

2006-06-27

Lee, Thomas (Department: 2115)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

Using delay

C713S503000

Reexamination Certificate

active

07069459

ABSTRACT:
A method and apparatus for adjusting clock skew involves using a plurality of oscillators distributed across the apparatus where at least one of the plurality of oscillators has a frequency dependent on a characteristic of the apparatus. A processor is arranged to adjust a bias generator dependent on the frequency. The bias generator is arranged to adjust a delay through a tunable buffer. The tunable buffer is arranged to propagate a clock signal dependent on the adjustment of the delay through the tunable buffer dependent on the bias generator.

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Stinson et al.; “14.4 A 1.5GHz Third Generation Itanium® Processor”; International Solid State Circuits Conference, 2003, Session 14/Mircoprocessor/Paper 14.4, Feb. 11, 2003; 6 pgs.

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