Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay
Reexamination Certificate
2000-06-26
2004-06-08
Lee, Thomas (Department: 2185)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
Using delay
C713S503000, C365S201000, C365S233100
Reexamination Certificate
active
06748549
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the field integrated circuits and, more specifically, the present invention relates to input/output (I/O) between integrated circuit chips.
2. Background Information
Currently, I/O timing tests of integrated circuit chips, such as central processing units (CPUs), are performed using testers. By using a carefully calibrated multi-channel tester, one can measure the I/O timing for all pins of a chip, where the testers and the on chip phase locked loop (PLL) circuits share the same clock. The specified I/O timings are acquired by exercising different “worst-case” patterns, which are programmed during the tester setup. Furthermore, the tester environment is designed to mimic “real world” system situations whenever possible.
There are several drawbacks to measuring I/O timings in the tester environment. In order to get very accurate readings, all tester channels require extremely tight timing and careful calibration, resulting in significant tester costs. Even then, a guard-band must be added to the measured timings to help guarantee specification numbers. This is to account for the uncertainties of strobe edges and clock skew introduced by the testers. The added guard-band in the specification numbers result in more stringent requirements for both circuit designers and system designers in order to reduce the number of unqualified defects.
Another problem associated with guard-band is that additional guard-band must be added to account for the difference between the tester and the real system environment because the measurements from the testers may not emulate the real system behavior effect on the I/O timing. Thus, the circuit designers, in many instances are burdened with the additional challenges stemming from the tester requirements.
When integrated circuit chips such as a CPUs fail I/O timing tests, the parts are typically discarded. In many instances, all other functionality of the chips that fail the I/O timing tests are within the specification requirements. In addition, it has been observed that in many instances, a significant portion of the chips that fail I/O timing tests fail by a relatively small margin.
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PCT International Search Report for PCT/US01/18754, May 30, 2002.
Sidiropoulos et al., “A Semidigital Dual Delay-Locked Loop”,IEEE Journal of Solid-State Circuits,vol. 32, No. 11, pp. 1683-1692 (Nov. 1997).
Chao Chi-Yeu
Kim Songmin
Lim Chee How
Taylor Gregory F.
Wong Keng L.
Blakely , Sokoloff, Taylor & Zafman LLP
Lee Thomas
Nieves Michael
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