Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay
Reexamination Certificate
2007-03-30
2010-10-05
Suryawanshi, Suresh K (Department: 2115)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
Using delay
C713S400000, C702S120000
Reexamination Certificate
active
07809972
ABSTRACT:
A data processing apparatus includes a first component for generating a signal operating in the first clock domain having a first clock period, and a second component for receiving the signal operating in the second clock domain having a second clock period. The second clock period is synchronous with but slower than the first clock period. Interface circuitry is provided for translating the signal between the first clock domain and the second clock domain, the interface circuitry operating in the first clock domain and comprising a storage element for temporarily buffering the signal generated by the first component before outputting that signal to the second component. Enable circuitry is used to control output of the signal from the storage element having regard to a specified input delay value identifying an input delay time of the second component expressed in terms of the first clock period.
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Broyer Pierre Michel
Tune Andrew David
ARM Limited
Nixon & Vanderhye P.C.
Suryawanshi Suresh K
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