Data bit-to-clock alignment circuit with first bit capture...

Details Data bit-to-clock alignment circuit with first bit capture... Data bit-to-clock alignment circuit with first bit capture...

2001-01-22

2004-03-09

Heckler, Thomas M. (Department: 2185)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

Using delay

Reexamination Certificate

active

06704882

ABSTRACT:

FIELD OF THE INVENTION
The present invention is a digital circuit for aligning or synchronizing the phase of the bits of a digital Data signal to a Clock signal.
BACKGROUND OF THE INVENTION
Computers and other digital data processing systems are typically formed from a number of components or subsystems. The operation of these systems requires the transmission of Data signals and Clock signals between the subsystems. In order for the subsystems to accurately process the Data signals, the phase of the Data signals must be accurately aligned or synchronized in time with the phase of the Clock signals. As these data processing systems become more complex and data and clock rates are pushed to ever higher levels, even relatively short differences in the length of the wires or other transmission paths between the Data and Clock signals can produce an unacceptable phase skew or misalignment between these signals.
Phase misalignments of the type described above between Data and Clock signals can be described with reference to FIG.
1
. In the example shown, the Data signal
10
is a time-varying waveform in which logic “1” bits are represented by a steady, relatively high voltage level and logic “0” bits are represented by a steady, relatively low voltage level. Sections of the signal
10
are overlaid on one another, with each bit beginning at the same relative location, to create the eye diagram
12
. Eye diagrams such as
12
are commonly used to illustrate the characteristics of signals such as
10
. As is evident from eye diagram
12
, finite periods of time are required for the signal
10
to switch between its two logic states. During these transition periods of time the logic states are not clearly defined (i.e., the voltage level is at neither the relatively high nor the relatively low level, but is instead somewhere in between).
Three different Clock signals
14
A,
14
B and
14
C are shown in relation to the eye diagram
12
in FIG.
1
. All the Clock signals
14
A,
14
B and
14
C have the same period and frequency, but are shown at different phase relationships to the eye diagram
12
. The phase alignment between the eye diagram
12
and Clock signals
14
A and
14
B has the Clock signals occurring during the period of time that the Data signals are changing states (i.e., during the transition region of the eye diagram). Under these circumstances a subsystem using one of Clock signals
14
A or
14
B to sample the Data signal
10
would be unable to accurately identify the correct logic state. To provide accurate sampling, the relative phase between the Clock signals and the Data signals should place the Clock signal near the center of the “eye” (i.e., during the stable region of the eye diagram). Clock signal
14
C, for example, is relatively well aligned with the Data signal
10
.
Circuits for aligning or synchronizing the bits of digital Data signals to Clock signals are generally known and disclosed, for example, in the following U.S. patents.
U.S. Pat. No.
Inventor
4,700,347
Rettberg et al.
4,756,011
Cordell
4,821,296
Cordell
5,081,655
Long
5,349,612
Guo et al.
5,400,370
Guo
5,778,214
Taya et al.
5,818,890
Ford et al.
5,822,386
Pawelski
Still other digital data processing systems extract the clock from the raw data stream. In systems of this type the clock recovery circuit outputs a clock signal which is not necessarily phase aligned with the data signal. Error rates in systems of this type can be relatively high.
Digital data systems generally rely on the phase synchronization between the digital Data signals and a common Clock signal distributed to all the major subsystems. As the clock frequency increases, the accuracy of the time alignment between the subsystems and their components becomes more stringent. Furthermore, as the number of subsystems and associated components increases in more complex systems, the ability to distribute an accurate Clock signal becomes more difficult
For these reasons there remains a continuing need for improved data bit alignment circuits. A data bit alignment circuit capable of being implemented entirely with digital logic would be particularly advantageous. A circuit of this type which is capable of effectively aligning the first bit of a Data signal to the Clock signal would be particularly useful. The circuit should, of course, also be accurate and capable of compensating for periodic drift between the relative phases of the Clock and Data signals.
SUMMARY OF THE INVENTION
The present invention is an efficient-to-implement data signal-to-clock signal phase alignment circuit which provides first bit capture capability. The circuit includes a data signal delay and sampling circuit, a comparator and decision circuit, and a multiplexer. The data signal delay and sampling circuit is connected to receive the data signal and the clock signal, and provides a plurality of time-slice bit samples of the data signal. The comparator and decision circuit is coupled to the data signal delay and sampling circuit, and compares and selects one of the plurality of time-slice bit samples which is phase aligned with the clock signal. The multiplexer is coupled to the data signal delay and sampling circuit and to the comparator and decision circuit, and outputs the selected time-slice bit sample as the phase-aligned data signal. Also included is an initial-bit intialization circuit connected to receive the clock signal and a data ready signal and coupled to the multiplexer. The initial-bit initialization circuit causes the time-slice bit sample corresponding in time to the data ready signal to be outputted as an initial one or more bits of the phase-aligned data signal before the comparator and decision circuit operates to compare and select one of the plurality of time-slice bit samples.


REFERENCES:
patent: 3588707 (1971-06-01), Manship
patent: 4359770 (1982-11-01), Suzuka
patent: 4700347 (1987-10-01), Rettberg et al.
patent: 4713621 (1987-12-01), Nakamura et al.
patent: 4756011 (1988-07-01), Cordell
patent: 4821296 (1989-04-01), Cordell
patent: 5081655 (1992-01-01), Long
patent: 5245637 (1993-09-01), Gersbach et al.
patent: 5349612 (1994-09-01), Guo et al.
patent: 5367542 (1994-11-01), Guo
patent: 5400370 (1995-03-01), Guo
patent: 5467464 (1995-11-01), Oprescu et al.
patent: 5537069 (1996-07-01), Volk
patent: 5708382 (1998-01-01), Park
patent: 5761254 (1998-06-01), Behrin
patent: 5778214 (1998-07-01), Taya et al.
patent: 5818890 (1998-10-01), Ford et al.
patent: 5822386 (1998-10-01), Pawelski
patent: 5872959 (1999-02-01), Nguyen et al.
patent: 5909133 (1999-06-01), Park
patent: 5945861 (1999-08-01), Lee et al.
patent: 6041419 (2000-03-01), Huang et al.
patent: 6108794 (2000-08-01), Erickson

Affiliated with

Also associated with

Rating

Data bit-to-clock alignment circuit with first bit capture... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Data bit-to-clock alignment circuit with first bit capture..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data bit-to-clock alignment circuit with first bit capture... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3241793