Data paths with receiver timing fixable to a downstream...

Details Data paths with receiver timing fixable to a downstream... Data paths with receiver timing fixable to a downstream...

2006-11-07

2006-11-07

Browne, Lynne H. (Department: 2116)

Electrical computers and digital processing systems: support

Synchronization of clock or timing signals, data, or pulses

Using delay

C365S189050, C365S194000

Reexamination Certificate

active

07134034

ABSTRACT:
A data path includes a downstream stage that strobes data at an input thereof responsive to a first control signal, an upstream stage that sends data to the input of the downstream stage responsive to a second control signal, and a control circuit operative to fix timing of the second control signal to timing of the first control signal. The data path may further include a second upstream stage that sends data to an input of the first upstream stage responsive to a third control signal having a timing with respect to the second control signal that varies responsive to a frequency at which data is transferred along the data path. A fixed delay circuit, e.g., a fixed delay circuit in a forward path of a DLL or PLL, may generate the first control signal from the second control signal.

REFERENCES:
patent: 5068831 (1991-11-01), Hoshi et al.
patent: 6011732 (2000-01-01), Harrison et al.
patent: 6061297 (2000-05-01), Suzuki
patent: 6192003 (2001-02-01), Ohta et al.
patent: 6226222 (2001-05-01), Park
patent: 6288953 (2001-09-01), Kwak
patent: 6757212 (2004-06-01), Hamamoto et al.

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