Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses – Using delay
Reexamination Certificate
2007-06-26
2007-06-26
Cao, Chun (Department: 2115)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
Using delay
C713S400000, C370S375000
Reexamination Certificate
active
10749613
ABSTRACT:
A method of synchronizing cyclemasters over a distributed bridge is disclosed. The method comprises: a local portal sending a synchronization signal to a peer portal through a bridge fabric upon occurrence of a cycle synchronization event on the local portal; the peer portal sampling its local cycle timer to obtain a sample value when the peer portal receives the synchronization signal; a bridge manager at an upstream portal communicating the sample value to a bridge manager at an alpha portal; the bridge manager at the alpha portal using the sampled time value to compensate for delays through a bridge fabric, calculate the correction to be applied to a cycle timer associated with the alpha portal, and correct the cycle timer.
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“Information technology-Microprocessor systems—Control and Status Registers (CSR) Architecture for microcomputer buses
Apple Inc.
Cao Chun
Gazdzinski & Associates
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